dumb question but is LVS supposed to fail on pin/net names that aren't the same? I ask because I run into problems with the fact that my xschem schematic uses bus_replacement_char = "xx", so bus names are BUSx0x, BUSx1x instead of BUS[0], BUS[1] (which was a trick I got from here to get our simulation working). This fails LVS for extracted ports in magic, like the gpio in user_project_wrapper where the names are just gpio[0]. Is there a way around this?

@Xiaochen Ni you can add lvs_ignore=1 to the netlist_options symbol. It will be ignored if you do a netlist with option

LVS->LVS netlist

enabled.

Ahh, wish i found that earlier

@Xiaochen Ni in many cases you need to add devices (like ideal sources, load capacitors and so on) that are only needed for simulation. Adding lvs_ignore=1 to these devices will make them disappear from the LVS netlist (which compares only physical silicon devices).

that is very useful to know

FYI, pins are matched by name only at the top level. Below the top level, as long as pins have a 1:1 correspondence, they will be considered to be matched regardless of the name. At the layout top level, there will be issues with chip integration if the pin names change.