hi @Mitch Bailey i don't know what is issue i am getting weird lvs error although pex is working. i have redesigned it multiple time on different pcs still getting same error. i have redesigned schematic too still this issue persist.

@Atif Khan 1. before you create the netlist from xschem, set

Simulation

->

LVS

->

LVS netlist: Top level is a .subckt

2. Add ports to the layout.

yeh i have done that still same error

Could you reshare the spice netlists and lvs results and the command that you use to run netgen? The schematic netlist should be

.subckt MUX1 VDD VSS IN1 IN2 VOUT SEL
...
.ends

not

**.subckt MUX1 VDD VSS IN1 IN2 VOUT SEL
...
**.ends

The extracted netlist should be

.subckt MUX_MAGIC SEL VDD VSS IN1 IN2 VOUT
...
.ends

not

**.subckt MUX_MAGIC SEL VDD VSS IN1 IN2 VOUT
...
.ends

i used netgen lvs MUX.spice MUX_MAGIC.spice

netgen will try to automatically match circuits with the same name. The results might be easier to debug if you change the layout cells to match the schematic names where you can. The schematic netlist has mosfet devices that are prefixed with

M

. These should be prefixed with

X

. I think you can add a

spiceprefix=X

property to the mosfet symbols.

ok let me try again. i think i had mistakenly removed this a moment ago while making top level subckt option enable otherwise spiceprefix option was by default set to X

Can you share the netlists that you used?

MUX.spice,MUX1.spice

@Atif Khan There’s no MUX1 subckt. Try netgen -batch lvs”MUX1.spice MUX” “MUX.spice MUX” $PDK_ROOT/$PDK/libs.tech/netgen/${PDK}_setup.tcl

IMG_4443.jpg

Looks like you need a space between the double quotes in MUX“”MUX1.spice

i tried

Much cleaner, I think. There are still sub cells with names that don’t match. For example, AND vs AND_MAGIC. If these are the same, I think you’ll get an even cleaner result. I’m guessing that the AND inputs are reversed. netgen checks which input is closer to power. Mos gate inputs aren’t swappable by default.

I have verified and input are not reversed also i swapped both.

Ok. Sorry for the run around. In addition to not swapping logic inputs, netgen does not reduce pseudo parallel gates. The AND layout contains 2 sets of series nfets (which are in turn, in parallel). The schematic only contains one set of series nfets. You can either change the schematic to match the layout or connect the two nodes internal to the series nfets in the layout

Can you elaborate, i am not getting why pseudo parallel gates appear.

Seems as though I was mistaken again. The internal nodes are already connected.

@Mitch Bailey I solved the error , my colleague had placed all transistor in flat, i created nand and then inverter it solved , i although it shouldn’t have raised issue. Thanks mitch