Hi all, I have a student who is doing some simple SPICE simulations of buffers meant to drive off-chip signals for 2.5D packages. She tried nangate45 and is consistently getting some odd (at least to me) results. When trying to achieve a beta ratio of 1, she often has to size the pmos to nmos 10:1, whereas I would think it is normally close to 2:1 for most processes. She is probably going to switch to Sky130 and try rerunning simulations, but I recall that there have been issues with the Sky130 spice models in the past for being unrealistic. • Does anyone have any experience in nangate45 and have an idea why the sizing difference might be so large? • Can someone confirm that the spice models for sky130 are realistic and can simulate large buffer chains? Thank you!

Weird. I may be wrong about what is that beta, but, usually, the difference in mobility for PMOS and NMOS is something about 3x. Maybe it is a huge deviation in VT that causes this 10:1 ratio. In my experience with sky130, it is ok to make inverters above 1 V supply with 3:1 ratio, but things get weird in weak inversion, with supplies below 0.5 V, and SF or FS corners. Anyway, sky130 models are BSIM 4 and real silicon was made using that. gf180 models are even more practical. I doubt nandgate45 can be more accurate than that.

Ok, we're looking at mostly upconverting nominal on-chip VDD to 1.8V for the off-chip buffer. If the sky130 model works well in that range, then I'll ask her to test that out. Thanks!

Are you talking about level shifters from core to IO voltages?

We will eventually develop the level shifters but right now we're looking at just single voltage supply (1.8V)

Well, what is really important in the end is rise and fall times, while dealing with PMOS and NMOS sizings. Are they too different if you use 10:1 instead of 2:1 to justify that?

Yes, the 10:1 is what she used to balance the rise/fall times. 2:1 ended up severely skewed.

https://github.com/google/skywater-pdk-libs-sky130_fd_sc_hs/blob/1d051f49bfe4e2fe9108d702a8bc2e9c081005a4/cells/inv/sky130_fd_sc_hs__inv_1.spice See here the sky130 inverter. It has some weird units. PMOS is 1.12/0.15 and NMOS is 0.74/0.15 um. But, most importantly, it uses a standard VT PMOS and a LVT NMOS.

The sizings I mentioned were for freePDK45. She hasn't tested sky130 yet.

Series? If the R was connected to ground, it could be a source of unbalance. This 10:1 ratio is really strange.

Here is the schematic if it helps

The designers of this sky130 standard cell library had to use different VTs to balance P/N. Maybe you could fix it by using a lower VT PMOS.

Thanks, that's some good food for thought.

A important thing about short length transistors, is that VT varies really wildly with any differences, and stabilize only for longer devices. You shouldn't mix different length devices for inverters, as the technology is tweaked for the minimum length. And, of course, models can behave badly for continuous increments.

Ah so I remember that discussion about the modeling. That makes sense. Thank you!

The models are continuous since I added the continuous models to the PDK. The issue with the models is that a number of the FET models are improperly characterized in subthreshold and have unrealistic behavior transistioning from above threshold to below threshold. If you are running a buffer chain, you should not be simulating in this region.

Thanks. No plans to operate in subthreshold region, mainly nominal VDD and above.

Ok, I correct myself. The models were discrete and now are continuous. Their problem were that if you make a parametric sweep with fine steps of length, they had discontinuities in its drain current when it jumped between model bins. My guess is that they are well characterized for the bin dimensions and the interpolation creates imperfections. And I've just downloaded FreePDK45 to check it. Its models are a single file without bins for level 54 (BSIM 4.0). No way it can model accurately different transistor lengths as sky130. I wouldn't use for anything with a length different to 45 nm.