Small status update on sky130 nmos for high-freque...
# analog-design
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Small status update on sky130 nmos for high-frequency applications and its correlation with the real world. MOS is a 32-finger, W=0.84um, L=0.15um. First, let me talk about RF modelling for the sky130 mosfets. For starters, there's no ready high-frequency model available at sky130 PDK, so if the designer would want to design at microwaves, or mm-waves, it would be necessary to add a series resistor to (each one of the) gate of your device, equal to 1/(5*gm). That lowers the Fmax of the base model to more than 500 GHz (!) to something more physical for a 130nm node, 150 GHz (red curve). That's the pure device Fmax. However, after adding the interconnection parasitics, this Fmax falls to 59.8 GHz (rose curve)... after further adding the GSG access parasitics, this falls further down to 55.1 GHz (lime curve). This seems really low, but has really good correlation with in-silicon measurements (49.8 GHz) (blue curve). So, we can extract two conclusions from this: 1. Magic does a really good job on contact parasitic extraction, I used extresist with C and CC parasitic capacitances and I'm really impressed with the good correlation between extracted view and silicon. 2. The high resistance LICON contacts and the high resistivity LI layer add so much series resistance to the mosfet that, even though the device itself has enough gain at mm-waves, the added extrinsic parasitics limit their high frequency application to microwaves or RF... I'm refining the EMx on the GSG pad parasitics to see if I can improve correlation between simulation and measurements, and I'm also working on de-embedding these pads directly from the measurements (in software). I'll keep you updated and I'll (eventually) feed my repo with the data. Slack Conversation
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Wonder, question, MIT LL SkyWater RH 90 and going to 45?
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@Art Scott skywaters RH 90 nm is an ITAR restricted Technology - so it will not become opensource ("RH" stands for radiation hard)
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Aloha Is there are non RH version? Mahalo
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I'd be quite happy with being able to get the SKY90 PDK under NDA, who would be the right person to talk to about costs?
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Troy, For SKY90 You would need to contact SkyWater directly and it would not be cheap. @Leonardo Gomes Have you considered double row contacts on the FETs. If the LICON resistance is so high as to completely dominate over the native device itself or the diffusion resistance then a double row of Diffusion contacts and LICON should provide a substantial gain. There is an area and capacitance cost but it is similar to an LDMOS device and you could read the extracted device paramaters and check that they are being captured correctly. You can also double contact only one side the FET if it is connected to VDDA or VSSA and see no increase in switching capacitance but get a real reduction in the device source resistance. This should also serve as a warning to anybody thinking of partially contacting their transistors. (You will see a very substantial degradation in both AC and DC performance).
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I think it's worth a shot even if it's on the basis of arriving at an "optimized" RF layout for sky130 fets. But I'm not very optimistic, LI and LICON are tens, if not hundreds of times more resistive than lower interconns and contacts on commercial cmos technologies. I mean, even comparing against sg13g2 there's an enormous difference. Even if had I laid out double rows everywhere the gain would have been marginal (and, yeah, this high resistivity LICON at source terminals serve as free degeneration, bringing the gain further down, and having high resistance at the gate would break the devices noise figure...)
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According to the 2022 Google blog, the Skywater 90nm is "based on MIT Lincoln Laboratory’s 90 nm commercial FDSOI technology": https://www.ll.mit.edu/research-and-development/advanced-technology/microsystems-prototyping-foundry/fully-depleted • (090SOI12) is the baseline CMOS process, a 90-nm FDSOI poly-gate process with an ultra-shallow trench isolation, both low-and mid-threshold-voltage transistors designed for use in digital and analog applications at an operating voltage of 1.2 V. This five-level metal technology is available in standard and radiation-hardened versions. Two additional thick-metal levels are supported for mixed signal and RF applications. All fabrication steps in the front end and back end of line are supported onsite.
https://semiengineering.com/near-threshold-computing-gets-a-boost/ (2022) "Retrofitting to older nodes The work done on the latest nodes directly benefits older nodes. “You can now bring the operating voltage closer to the transistor threshold voltage to save power,” says Bautz. “In essence what you’ve got now is a legacy node, from a delay calculation perspective, that behaves like a very advanced node. But from a delay calculation perspective, those same models come to bear and enable that approach. This is something we’re starting to see at various fabs, and with customers, trying to push this envelope of threshold voltage to operating voltage.” Am curious whether improvements on the newer nodes could be applied to 130nm and 90nm