The second approach is to use a geometric approach, to increase the size of the inverter cells in a buffer chain until it works. You can work with the extracted metal route or even use something fancier, as sp parameters. If you can, you split the route and insert buffers midway. Generally you cannot. Of course, the custom design of buffer from a clock synthesis block to other inside chip is very different from RX and TX drivers.

Anyway, for new technologies, the transistor gate capacitance is a very small part of the total input capacitance. Routing is much more troublesome. Even power supply lines are a big problem.