Thanks for the answers. Basically what I want to do is transistors sizing for delay optimization in a real project using logical effort method.So my idea is first to do a crude hand calculation, feed the transistors size found to my spice circuit model and then try to tune the results with the simulator. Is it the correct approach or have I to apply the logical effort method starting from values estimated from the simulator as above suggested? I searched a lot on internet how companies in real world perform circuit transistors sizing but I didn't find anything. Unfortunately hardware is still a closed world contrary to software where I come from.

Normally, what you have in the industry is the smallest inverter gate possible in the technology as the base load and driver. The other inverters with more driving capabilities are just geometrically wider. The rest of the other logic gates are a bit more complicated, but they are classified as their driving capability to the base load inverter. Nothing fancy. This is how standard cells are classified, as integer numbers as multipliers. Now, if you are talking about longer wires connecting gates, where their load is comparable to logic gates' input capacitances, then you should do some calculations to optimize a circuit. Anyway, you need to calculate and optimize logic gates only for custom circuits. Physical synthesis software is your friend.

The method I outlined is the usual approach for logical effort design. You can also find parasitic delay terms, etc. in a similar way. Refer to the attached material. Using parameters out of the spice model can be fine for small signal analysis, but makes little sense for accurate digital delay calculations.