Just curious about the noise performance / modelling of this process. Does anyone have a feel for how accurate the noise models are vs post silicon results? Overall how does this process compare to other similar processes? Did the SW130 fab used to be the Cypress Semi fab? I'm considering taping out a low noise ASIC in this process and want to get a feel for noise performance of this process, before I commit. Be great to hear from anyone who has taped out low noise designs in it.