I'm trying to apply the linear delay model as described in Harris and Waste book to Skywater130 node. All numerical calculations are based on the value of the gate capacitance defined as (pag 69 in the 4th edition of the book) Gg=Cox*Lmin * W where: Cox = Gate oxide capacitance Lmin= channel min transistor length W = transistor width. Can someone tell me the value of Cox (gate oxide capacitance) ? Is it correct to assume the minimum dimensions of sky130_fd_pr__nfet_01v8 Wmin x Lmin = 0,42 x 0,15 um ?

The best way to get this value: Build two inverter chains, one is loaded with another couple of inverters, the other is loaded with a fixed capacitance that you adjust iteratively. You have found the effective cap value of your transistors when the two delays are the same. Cox is not a good number to use if you want your model to be reasonably accurate for delay calculations.

You can find tox here, in the transistor models: https://github.com/google/skywater-pdk-libs-sky130_fd_pr/blob/f62031a1be9aefe902d6[…]b57627436/cells/nfet_01v8/sky130_fd_pr__nfet_01v8__tt.pm3.spice + toxm = 4.148e-9 Then you can calculate Cox as explained here: https://www.edaboard.com/threads/how-we-calculate-cox.56511/ However, this Cg formula is just a crude estimation. The ring oscillator method Prof. Murmann told is more useful. You can also run an op simulation and list the transistors Cgg, of even run an AC sim and see the input capacitance. Just be aware that the input capacitance varies with the transistor's biasing point.