For the LVS report: (1) Ignore the property error. Or you can adjust the netgen setup deck to have netgen ignore the "pj" property on the diode. I think the schematic is not defining "pj", or might be specifying it as "perim". (2) test_io was hastily put together. It does not define pins, which is why you get a pin mismatch at the top level. You should probably just compare the "minesd_pad_and_pg" cell by itself. Or in this case, don't instantiate "test_io" in your design, but instantiate the pad. However, such errors resolve at the next hierarchy level up, so it's not a fatal error. (3) There are cells which I assume are yours, like "ROIC_align". . . They need defined ports. Without defined ports, you will always get pin mismatches and the cell will get flattened into the next level of hierarchy. At the hierarchy top, that will make it harder to debug. (4) I'm a bit bothered by entries on the schematic side like "|PMOS_S_61436961_X10_Y1_1712773682[[0]]". The "[[0]]" at the end indicates that netgen has seen multiple cells with the same name and is trying to disambiguate them. (5) Start debugging with things that are easier to track down. In the summary of user_analog_project_wrapper, the schematic side says that there are two independent MiM caps. The layout side says that there were two MiM caps merged into one because they were found to be connected in parallel. Seems like a good place to start.