@Tim Edwards FWIW, found a verilog netlist with these signals

wire \NEURON_WRAPPER.SCI_SLAVE.NEW_REQ_DETECTOR.SAMPLE_IN ;
 wire \NEURON_WRAPPER.SCI_SLAVE.NEW_REQ_DETECTOR.sample_in ;

netgen shorts them because I read the spice standard cell library first and thus ignore case. I don’t suppose it would be possible to have the verilog portion of the netlist case sensitive and the spice portion case insensitive. 🤪

There probably is a way to do this by tracking net names within a verilog file and forcing a renaming of any nets that are case-mismatched. I have never given that any consideration before.

Ok. I’ll log an issue then and let you do your magic.

Why do people do this?? Its not the first time I've seen tools fail on such.

@Matt Liberty right!? I suppose it may be inevitable when multiple people are designing the same circuit. Definitely a “gotcha”.

Some linter should complain about such things long before you get to physical design

Definitely. @Matt Liberty Are you of the opinion that spice should flag case conflicts too also (or just verilog).

Its legal in each language but doesn't work in combination. I think Verilog should complain as it is typically upstream and the source of the mixed-case conflict