@Mitch Bailey Hello, Mitch. I'm doing LVS with standard cells of gf180mcu as you advised to use cell library. However, during LVS, LVS seems not to read the cell library(gf180mcu_fd_sc_mcu7t5v0) as I think spice netlist have "XM" mosfets rather "M"mosfets. As shown below, there are netlists extracted from netlist, but no standard cell netlist, but only analog part transistors like diff pair, current source, etc. Could you gimme advice? +) I'm not sure the way I linked DVDD and DVSS with standard cells

magic and netgen LVS use the

XM

devices which are the same as those used for simulation. I think klayout extracts

M

devices. Instead of the spice library, try the cdl library

libs.ref/gf180mcu_fd_sc_mcu7t5v0/cdl/gf180mcu_fd_sc_mcu7t5v0.cdl

@Mitch Bailey As you said in a previous thread(https://open-source-silicon.slack.com/archives/C032Y8J3KHA/p1711540346056319?thread_ts=1711371126.176209&cid=C032Y8J3KHA), is copying a local version of the cell spice only way to use spice library? • when we use spice library ◦ LVS can't read • when we use cdl library ◦ xschem can't read (https://open-source-silicon.slack.com/archives/C04MJUYP99V/p1712075711757899)

Looks like you’ll need to use the spice library for simulation (you only need to include it in the test bench circuits) and the cdl library (without the diodes) for LVS. Not an optimal solution, but I don’t know that anyone is working on a better solution.

@Mitch Bailey Thanks! I will try!

I think the klayout rules short all connections to psubstrate. You could try naming both

VSS

and

DVSS

as

VSS

. I think you’ll get a warning, but it might pass LVS.

@Mitch Bailey Thanks a lot. no warning happened. I named both VSS and DVSS as VSS in the schematic netlist and layout metal label. Any guardring for digital blocks is needed?

@Junbeom Park guardrings are not needed, as such, since you have taps. You might consider placing tap cells

gf180mcu_fd_sc_mcu7t5v0__filltie

instead of hand drawing tap connections.

I will try!