Hi, I'm have problems doing lvs with magic and netgen on some sections of the ota. In the nmos current mirror

cm_nmos

, after parallel/series merging the schematic contains 3 nets and layout 4. While on the small resistor

ota_res

there's the same problem but also a fanout one. Both designs are lvs and drc clean with klayout. I'm worried that if netgen doesn't validate it, that could cause problems for me when post-simulating. How can I debug this kind of problems? The attached zip file has a makefile. To run lvs do

make problem-lvs

@aquiles viza Thanks for the detailed test results. 1. The openlane and related LVS tools specify the layout first and schematic second. It’s not wrong to do the opposite, but can be confusing. 2. the

cm_nmos

circuit is showing this error

Net: vss                                   |Net: vss                                   
  nfet_03v3/(1|3) = 5                      |  nfet_03v3/(1|3) = 5                      
  nfet_03v3/2 = 1                          |  nfet_03v3/2 = 1                          
  nfet_03v3/4 = 4                          |                                           
                                           |                                           
(no matching net)                          |Net: 0                                     
                                           |  nfet_03v3/4 = 4

which means that the psubstrate in the layout is not connected to anything. klayout’s rules label the substrate without requiring a connection. (very scary if you ask me.) You can either add a substrate contact (preferably more than just one) or wait until the substrate contacts are included in a higher hierarchy. 3.

ota_res

is similar

Net: vss                                   |(no matching net)                          
  ppolyf_u_1k/3 = 2                        |                                           
  ppolyf_u_1k/(1|2) = 2                    |                                           
---------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------
(no matching net)                          |Net: 0                                     
                                           |  ppolyf_u_1k/3 = 2                        
                                           |                                           
(no matching net)                          |Net: vss                                   
                                           |  ppolyf_u_1k/(1|2) = 2

The

ppolyf_u_1k

resistor is extracted as a 3 terminal device with the 3rd terminal being the unconnected substrate (used for capacitance calculations, I think). Either add a psub contact or ignoore it until the higher hierarchy.