Slackbot
10/05/2023, 11:53 AMDanielle Marinese
10/16/2023, 1:44 PMHarald Pretl
10/16/2023, 5:10 PMBoris Murmann
10/18/2023, 3:18 PMBoris Murmann
10/18/2023, 3:19 PMBoris Murmann
10/18/2023, 7:33 PMDanielle Marinese
10/19/2023, 7:30 PMmehdi
10/22/2023, 9:48 PMMohammed Fayiz Ferosh
10/23/2023, 2:05 AMBoris Murmann
10/23/2023, 2:53 PMHarald Pretl
10/23/2023, 6:18 PMngspice
. For this he has prepared an example of a 3b Verilog counter tied to a 3b R-2R DAC (just to have a super simple example). Graphing in xschem
is included as well. We will give you all files after the Chipathon meeting.Danielle Marinese
10/26/2023, 4:05 PMJunbeom Park
11/01/2023, 10:21 AMJørgen Kragh Jakobsen
11/01/2023, 4:04 PMi229904 Ahmar Habib
11/02/2023, 7:43 AMmehdi
11/03/2023, 10:29 PMGabriel Maranhão
11/08/2023, 3:18 PMGabriel Maranhão
11/08/2023, 5:06 PMGF180mcuD
? If so, there will be needed some modifications to the IO PADs?
Klayout layers for GF180 are a little hard to visualize, I changed the .lyp
file and had to modify a lot of layers to better visualize them, I hope that is OK.Mitch Bailey
11/10/2023, 3:31 PMDanielle Marinese
11/16/2023, 4:08 PMDanielle Marinese
11/16/2023, 4:08 PMaquiles viza
11/17/2023, 4:58 PMaquiles viza
11/17/2023, 9:27 PMDanielle Marinese
11/20/2023, 5:34 PMSlackbot
11/22/2023, 7:53 AMmehdi
11/22/2023, 3:28 PMJunbeom Park
11/22/2023, 4:14 PMaquiles viza
11/22/2023, 7:17 PMZhiyang Ong
11/26/2023, 7:20 PMmehdi
11/27/2023, 4:40 PM