Hi @Tim Edwards I have one question regarding the input offset voltage calculation. In

sky130_ef_io_instramp/cace/input_offset.sch

, the offset voltage is calculated from the transient simulation which does include the effect of the propogation delay in it. What if the offset voltage is calculated using the DC simulation with the same method :

(inp - vcm when out = vdd/2)

? And the propagation delay can be calculated from the transient simulation. Will that be incorrect? Sorry I am just confused.

Define "correct", please.

@naina singhal: The testbenches I have in

sky130_ef_ip__instramp

were originally used with a bandgap circuit; I did not try to rewrite them for the example. Bandgaps have metastable states, so DC and AC analyses can land in the wrong state and give the wrong result. The transient analysis is used to ensure that the bandgap startup circuit puts the circuit in the correctly operational state. For circuits that don't have metastable states, a DC analysis is appropriate (and preferred) for input offset. So you have the right idea. The confusion comes from looking at a testbench that works but which is not the best choice for the application.

Folks … in principle, commits like https://github.com/tatzelbrumm/sky130_ak_ip__cmos_vref/commit/fc8994ee722ea29fa9613e97d553460ddbd514e8 https://github.com/tatzelbrumm/sky130_ak_ip__cmos_vref/commit/79148019fdb6e8b41da58efed55dcc601830c612 should kick a reference circuit into the correct attractor state, but CACE, together with the inconsistencies where to find the sky130 libraries, are a very effective chokepoint to prevent me from reviewing others' designs any more than by visual inspection. (At least by reviewing others' submissions, I hope to learn enough about setting up CACE and avoiding its undocumented, subject to change without notice, pitfalls, to have something that looks like a working data sheet, never mind whether or not the specs are actually meaningful)

@Tim Edwards Thank you so much for explanation. 🙂