Hi, I want to simulate my design with GPIO pads. I will be connecting my pin to analog GPIO. Is there a way to simulate the complete design to simulate leakage, parasitic resistance etc? @Mitch Bailey I cloned the

sky130_fd_io

from

<https://github.com/d-m-bailey/sky130_fd_io.git>

but I can not find a correct way to connect it for analog pad connection. Can you please tell me the correct connection?

@naina singhal currently, the only pad that I created a schematic for is

top_gpiov2

. Are you talking about the analog connection to this pad or to the analog only pads used in

caravan

? There are analog only pads in

caravan

, but I wouldn’t call those analog gpio (general purpose i/o). If you’re using the analog connections to

top_gpiov2

, the connections for

caravel

are

analog_io[28:0]

and these correspond to

gpio[35:7]

and connect to the

PAD_A_ESD_0_H

(which has a 250ohm resistor) pin of

top_gpiov2

. If you’re using the analog connections to

top_gpiov2

with caravan, the connections are a little more complicated. For

user_analog_project_wrapper

, the analog connections are

gpio_analog[17:0]

(same connections as

analog_io

in

caravel

) or

gpio_noesd[17:0]

which bypass the 250ohm resistor and connect to

PAD_A_NOESD_H

of

top_gpiov2

.

@Mitch Bailey Thank you so much for your answer. I am going to use the caravan wrapper. There are

gpio_analog[17:0]

present there with ESD protection. What about the other pins? (io_in, io_out, io_oeb, io_in_3v3, gpio_noesd). What is a proper connection for them?

io_in

,

io_in_3v3

are irrelevant. If your gpio configuration is

GPIO_MODE_MGMT_STD_ANALOG

, you don’t need to worry about

io_out

or

io_oeb

for the gpio with analog connections. However, the

io_out

and

io_oeb

signals for

gpio[6:0]

(no analog connections) are buffered, so it’s probably a good idea (and shouldn’t hurt) to tie all these signals either high or low. You should leave

gpio_noesd

unconnected if using

gpio_analog

.

Ok. Thank you very much @Mitch Bailey]

The schematic matches the layout according to LVS, but doesn’t contain any parasitics.

@Mitch Bailey, I tried simulating the pad with my circuit but it is not working. Is the schematic only for LVS?

I have not used the schematic for simulation, but others have used the extracted layout for simulation (and LVS says that they are electrically the same). I’m not exactly sure of what each pin is for but you can find the details here.

Ok @Mitch Bailey. Thank you so much for the details.