Hello, everybody. I'm currently designing a operational amplifier, and I'm using cascode miller compensation. The open loop simulation results show a 4 MHz GBW and 69° phase margin. However, for a voltage follower configuration, when I run a transient simulation for a step input signal, I'm seeing ringing. Why? The github repo is at https://github.com/lhrodovalho/sky130_rodovalho_ip__lpopamp/ and the testbenches are in the xschem folder.

@Luis Henrique Rodovalho Stand by, I'm so gonna fork your $STUFF: https://github.com/tatzelbrumm/sky130_rodovalho_ip__lpopamp/tree/tatzelbranch (I spent a ridiculous amount of time lately to try and get your non-CACE test benches to run, because they're EXTREMELY instructive what you can do with ngspice alone)

@Christoph Maier It's still incomplete. I need to automate plots and make the monte carlo sims.

@Luis Henrique Rodovalho Wellll … I thought I had more important stuff to do (understand how you get things done without CACE) than to set up my own test benches, and my design review is in 2 hours from now.

ngspice alone can't do multiple corner sims. In my case, I couldn't make CACE work, so I used scripts to generate multiple spice files, and replacing some tags with the right corners and parameters, then I run it and its ok. CACE does something like that too, as it generates multiple files for each corner. See this testbench https://github.com/lhrodovalho/sky130_rodovalho_ip__lpopamp/tree/main/ngspice/tb_lpopampa_open_ac Inside the include folder there is a TCL script to generate a corner list. There is a gen_tb.tcl script, which actualy generates the .sp files in the spice folder.

@Luis Henrique Rodovalho: It is possible for ringing to be a simulation artifact; does it vary with minimum transient step size?

@Tim Edwards Looks too much like a "real" damped oscillation to be a simulation artifact. Should depend on the 2nd pole (capacitive load, or even resistive load; this is a 2-stage Class AB amplifier, anyhow, and a bit tricky to compensate, because it needs two Miller capacitors for compensation, across both the nmos and pmos output transistors). If I "pass" the review, I'll take a look at it — haven't figured out corner analysis yet, anyhow, and the Moreira de Lima design is, to my knowledge, the best available example among the chipalooza submissions for me to figure it out, eventually.

Here are the results for 100 mV and 1 V step input amplitude. Ringing and overshoot decreases and then fades. Large signal results are weird.

Just thinking out loud here - but maybe the way that the loop-gain is being measured is not quite correct? When using cadence, I typically use a stability analysis with an iprobe to break the feedback loop. My understanding is that the iprobe block breaks the feedback loop while maintaining the impedances seen at either side of the iprobe. So, while in theory measuring open-loop ac response should be the same (or close) to loop-gain in unity-gain configuration, the open-loop setup might not be taking into account capacitive loading from the inverting terminal. My guess is that if capacitive loading at your inverting terminal is large enough, it could move your second pole lower, reducing phase margin and giving you the ringing that you see. I suppose the fix might be to assume a larger load capacitance (maybe like 31pF) and compensate for 70 deg PM in that situation?

I agree with Thomas. Is the load capacitance the same in both open- and closed-loop sims? I would at least try to add the equivalent of one input transistor’s worth of gate capacitance at the output of the opamp in the open-loop sim to see how much it drops the phase, just as a quick way to debug, before diving into Middlebrook analysis.

I agree that getting the closed-loop PM is the answer. Is there an equivalent to stb analysis in ngspice? Do we have to do Middlebrook manually (two testbenches + postprocessing)?

Also, with this opamp topology there will be at least two gate capacitances, because there are two differential pairs used for input rail-to-rail operation. This would make the difference between open-loop analysis and loop-gain analysis even larger.

And just eyeballing the open-loop Bode plot, right around 4MHz the phase changes quickly, so a relatively small error in estimating the effective load can result in a relatively large measured phase difference. Possibly enough to cause it to be under-damped when the loop is closed.

You need more than 76 degrees phase margin to avoid ringing. Also try to set .option method=gear to exclude the possibility of numerical oscillations.

And again just eyeballing the amount of overshoot in the 10mV step response plot, which is about 5% i.e. 0.5mV for a 10mV step, it translates to 65 degrees of phase margin. So you’re really not that far off.

The cascode compensation approach tends to sneak in complex poles, which make the usual two pole assumption for required phase margin a bit iffy. I agree that you are not far off.

@Boris Murmann, is there anywhere something like a "confession session" article what tends to go wrong with the compensation method as originally published by Hogervorst … Hujsing in 1994? Usually, only the successes make it to publication, and the sometimes even more instructive failures end up in the equivalent of the

.gitignore

.

@Christoph Maier I think one of the more comprehensive papers that derives the complex conjugate pole pair is: P. J. Hurst, S. H. Lewis, J. P. Keane, F. Aram and K. C. Dyer, "Miller compensation using current buffers in fully differential CMOS two-stage operational amplifiers," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 51, no. 2, pp. 275-285, Feb. 2004, doi: 10.1109/TCSI.2003.820254. I am also attaching some of my old lecture notes, which try to argue conceptually why this compensation approach is prone to complex conjugate poles in the inner feedback loop (see slides 53+).

@thread_followers you may find this lecture interesting regarding the relation between PM and ringing/peaking