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<@U02ND5R1SAW> <@U01819B63HP> <@U016EM8L91B> I was...
# reram
v
@Barak Hoffer @Stefan Schippers @Tim Edwards I was trying to programme the 1T1R module with ReRAM. After forming, the LRS state is not reaching upto 10k as per sky130 pdk. Resistance ranges in Mohms(3.24Mohms to 3.12Mohms). I have given wl(1.4 - 2.0 (0.1 step) for forming and kept 2v for reading), bl(3v for forming and made 0v for reading), sl(0 for forming and 0.1 for reading). Pulse width 1000ns for both forming and reading. Please give feedback regarding the programming voltage applied for forming and reading.
a
Firstly, I don’t think the ReRAM model captures FORMing process. I can see that the SET process is maybe happening correctly. What exactly do you mean by LRS not reaching up to 10k? Do you mean 10 kOhms? If so, where exactly are you measuring that resistance in the plots you have sent? I only see you doing some voltage divider measurement 
(out2-out1)/v3
, but that is not the correct formula for resistance… the correct formula is R=V/I. I don’t see any currents included in your plots
Or are you trying to do a voltage-based resistance measurement with a shunt resistor?
If so, I think your formula is still wrong. If you check the units of 
(out2-out1)/v3
it is unit-less not in units of ohms or siemens
a
The v3#branch refers current through v3 source node. out2-out1 measures voltage difference between reram.
a
I’m not familiar with that notation and I’m not sure that’s correct. Typically, I have seen the notation for current through a node to be done like 
I(v3)
Mostly because the numbers do not make sense. I would try replacing 
v3#branch
with 
I(v3)
a
Can we get current from particular node/element in ngspice? I couldn't see an option like I(R2).
a
I(R2) = I(V3) in this case
v
I have interchanged the terminals and applied 2.6v in SL and 0v for BL and 2.5v in WL .And tried to read for measuring HRS ,for that 0.7v(Threshold voltage to keep transistor ON) tom WL ansd 0.1v to Bl and 0v to SL.I have measured resistance using R=V/I.
a
I have few concerns for that,
Do we need to perform forming in simulation to get HRS as 10Mohms? Also according to the table provided in the documentation, wl is fixed for reset operation, is that correct? And giving threshold voltage to keep transistor ON for reading. Please verify whether it is correct way of applying the terminal voltages
a
There is no FORMing in simulation afaik
You can increase WL for RESET if you want but it does not affect the final resistance much. For SET, it affects the final resistance pretty significantly, because the select transistor acts as a series resistor, and when the resistance of the RRAM drops, it basically limits the current. This acts as a self-limiting process. That doesn’t happen for RESET since it is a “runaway” process where the select transistor has lower and lower voltage drop as the process happens.
Generally speaking, RESET is a harder process to control for this reason. I recommend using SET to tune the resistance and RESET to go back to HRS
BTW the Verilog-A RRAM model is not designed for fine-grained resistance tuning. As you can see, there is a pretty abrupt drop in the resistance when SET happens. It might be pretty difficult to get that to work in simulation, though you can do it properly with a real device
Generally speaking, these models are just to get you started and won’t correspond very well to what you will see in practice
In my experience, it is better to explore things like programming algorithms post-silicon
a
Thank you for these details. I want to analyse the system behaviour in terms of number of stable conductace states available, how many pulses needed to change the state from a co ductance states to another state, reliability, endurance. Can i get these information before fabrication?
a
no, not from simulations
There is a bit of information in some publications on these though
I recommend this one for such details, which was a chip I worked on and the first tapeout of RRAM on SKY130
a
Thank you for the details, I have gone through this and i was trying to create circuit for forming and set reset operations. I got to understand that we can program the device using either applying definite number of pulses or varying amplitude of the pulses, I found changing voltage amplitude is used for set or reset programming in above paper. Can i change frequency rather than amplitude?
a
Yes. You can change pulse width (inverse of frequency) as well.
It isn’t as effective as voltage modulation, but you can do it for sure
a
That is a good option, thank you for suggestion. How many states can we get for 1T1R?
a
4-8 depending on how long you want retention for
You can even do more but they will not last very long
a
4-8 is very good number. During the read operation we need to apply 0.1-0.2 voltage to SL right? and threshold voltage to WL. We can read through BL. is that the way post silicon verification performed?
Did you try to integrate the forming, set and reset inside the chip inself?
a
0.1-0.2 V on either BL or SL will do the trick. Whichever you pick, the other side should be at 0V. For WL voltage, you typically want to be significantly above threshold voltage to get better SNR. I used 2.5-4V in SKY130 for WL, you can play around with it. When you say integrate FORM/SET/RESET inside the chip, you mean have on-chip drivers? No, I did not do that, but it is possible to do. I did it for a different ReRAM chip taped out in a different technology (40nm). It’s a bit more challenging because you have to build and verify a lot more peripheral circuitry, including DACs/ADCs. I don’t recommend it for your first ReRAM chip, especially if you’ve never designed a robust DAC before.
a
Yeah..thats true. So we have to use 5v nfet for 1T1R right?
For giving WL as 4V
a
You can either use a high-voltage (5V) FET or you can go with a core FET at lower operating voltage and overdrive it. We weren’t sure which would work, so we taped out multiple arrays. They both worked fine.
a
Can we have 5v vdd available?
a
?
a
In caravel we can not get 5v vdd power rail right?
t
@Aswani AR: Of course you can. All I/O is rated up to 5.5V.
✅ 1
a
There are io_analog, gpio_analog(both are 5v i think), what about io_in or io_out or io_3v3 and io_oeb? These are multiplexed if i am not wrong
@Akash Levy For reram set and reset operation, according to the table provided in the website(https://sky130-fd-pr-reram.readthedocs.io/en/latest/technology_specifications.html#forming) we need to give a series of 1000ns pulses to both wl and sl, is it a trail and verify method or can we set the number of pulses need to be applied before?
t
io_in
, 
io_out
, and 
io_oeb
are all 1.8V digital signals. 
io_in_3v3
is the same voltage as 
vddio
(nominally 3.3V, but can be as high as 5.5V).
a
Thanks @Tim Edwards for answering the first question. For the second question, you should do write-verify because the RRAM behavior is random and won’t do the same thing each cycle. Using a fixed number of pulses will not give you well-controlled distribution of final resistance.
a
Is that reram should be connected to drain terminal of mosfet? Can i connect source to reram TE and bl to BE of reram, I just want to clarify before completing layout? Few papers recommend connecting reram BE to dran.
a
I think drain should be connected to BE and BL to TE
image.png
This is from our 2019 paper on SKY130 ReRAM, so I’d do it this way to be safe. I’m pretty sure you can make it work either direction, but better to stick with something that’s been done before
a
Thats good..for applying negative voltage. Is there any pin restriction or can i use any analog io pin?
t
@Aswani AR: If you want to apply negative voltages, you will have to use the Caravan chip, and any of the 11 analog straight-through pads will work. You will probably want some ESD diode on the high side, as long as the negative voltage doesn't exceed the diode reverse breakdown. Ultimately, you'll have to treat the pin as ESD-sensitive and be careful handling the chip.
a
Is there any restriction to use GPIO25 and GPIO26 ..??
t
Yes. You may not apply a voltage below VSSIO or above VDDIO to any GPIO pad. On Caravan, the only bare analog pads are 
mprj_io[14]
to 
mprj_io[24]
. So 
mprj_io[25]
and above are regular digital/analog GPIOs and have ESD diodes to VDDIO and VSSIO that must not be forward biased.
a
I would avoid applying negative voltages to any part of the 1T1R structure. For SET, you can apply positive voltage at BL and ground SL. For RESET, you can apply positive voltage at SL and ground BL.
Is there any particular reason you want to use a negative voltage as opposed to this approach?
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