https://open-source-silicon.dev logo
Join Slack
Powered by
Hi all, i'm working on a eFPGA and i have some LVS...
# lvs
e
Hi all, i'm working on a eFPGA and i have some LVS precheck errors, how can i check and solve those errors? These are the reports generated by the precheck.
21_FEB_2024___22_19_00.zip
m
@Emilio Baungarten before I look at the LVS logs, I noticed there was a warning on the oeb check. From the 
logs/OEB_check.log
Copy code
gpio |   in   |   out  | analog |  oeb min/sim/max  | Message
  30  |    320 |        |        | vssd*/vssd*/vssd* | Warning: oeb expected high for input only
  31  |   1892 |        |        | vssd*/vssd*/vssd* | Warning: oeb expected high for input only
The 
io_in[30]
(
reset
) input is connected to 320 devices and 
io_in[31]
(
clk
) is connected to 1892. Maybe you are still in the initial stage of floorplanning, but you’ll probably want to buffer these inputs and use clock trees. I don’t know how to do that with your layout, though. LVS is missing the gate level modules or spice subcircuits for these cells
Copy code
cbx_1__0_ 
cbx_1__10_
cbx_1__1_
cby_0__1_
cby_1__1_
cby_8__1_
grid_clb
grid_io_bottom
grid_io_left
grid_io_right
grid_io_top
ioenb
sb_0__0_
sb_0__10_
sb_0__1_ 
sb_1__0_
sb_1__10_
sb_1__1_
sb_8__0_ 
sb_8__10_ 
sb_8__1_
You can add these to the 
lvs/user_project_wrapper/lvs_config.json
file in the 
LVS_VERILOG_FILES
list.
Copy code
"LVS_VERILOG_FILES": [
                "$UPRJ_ROOT/verilog/gl/cbx_*.v",
                "$UPRJ_ROOT/verilog/gl/cby_*.v",
                "$UPRJ_ROOT/verilog/gl/grid_*.v",
                "$UPRJ_ROOT/verilog/gl/ioenb.v",
In the latest version of netgen, the order is not important, but precheck may be using an older version, so list the lower modules first.
Your CVC(RV) results are showing tristate signal output to buffers and tristate buffers. This is caused, for example, when only one tristate buffer drives an input to non-clocked logic. When the tristate buffer is disabled, the input to the logic will be Hi-Z which can result in current leaks and unexpected results. Tristate signals into tristate buffers are ok if the second tristate buffer is always disabled when the first tristate buffer is disabled. Here’s a list of the signals (62) with possible Hi-Z output and the corresponding cell (96) where the error is detected. If the signal’s tristate output buffer is never disabled, there is no problem.
Copy code
/grid_io_bottom_0_top_width_0_height_0_subtile_0__pin_inpad_0_ /Xsb_7__0_(sb_1__0_)/Xinput31(sky130_fd_sc_hd__buf_1)
/grid_io_bottom_0_top_width_0_height_0_subtile_0__pin_inpad_0_ /Xsb_8__0_(sb_8__0_)/Xinput20(sky130_fd_sc_hd__clkbuf_1)
/grid_io_bottom_1__0_/gfpga_pad_GPIO_PAD /Xgrid_io_bottom_1__0_(grid_io_bottom)/X_7_(sky130_fd_sc_hd__ebufn_8)
/grid_io_bottom_1_top_width_0_height_0_subtile_0__pin_inpad_0_ /Xsb_6__0_(sb_1__0_)/Xinput31(sky130_fd_sc_hd__buf_1)
/grid_io_bottom_1_top_width_0_height_0_subtile_0__pin_inpad_0_ /Xsb_7__0_(sb_1__0_)/Xinput29(sky130_fd_sc_hd__clkbuf_1)
/grid_io_bottom_2__0_/gfpga_pad_GPIO_PAD /Xgrid_io_bottom_2__0_(grid_io_bottom)/X_7_(sky130_fd_sc_hd__ebufn_8)
/grid_io_bottom_2_top_width_0_height_0_subtile_0__pin_inpad_0_ /Xsb_5__0_(sb_1__0_)/Xinput31(sky130_fd_sc_hd__buf_1)
/grid_io_bottom_2_top_width_0_height_0_subtile_0__pin_inpad_0_ /Xsb_6__0_(sb_1__0_)/Xinput29(sky130_fd_sc_hd__clkbuf_1)
/grid_io_bottom_3__0_/gfpga_pad_GPIO_PAD /Xgrid_io_bottom_3__0_(grid_io_bottom)/X_7_(sky130_fd_sc_hd__ebufn_8)
/grid_io_bottom_3_top_width_0_height_0_subtile_0__pin_inpad_0_ /Xsb_4__0_(sb_1__0_)/Xinput31(sky130_fd_sc_hd__buf_1)
/grid_io_bottom_3_top_width_0_height_0_subtile_0__pin_inpad_0_ /Xsb_5__0_(sb_1__0_)/Xinput29(sky130_fd_sc_hd__clkbuf_1)
/grid_io_bottom_4__0_/gfpga_pad_GPIO_PAD /Xgrid_io_bottom_4__0_(grid_io_bottom)/X_7_(sky130_fd_sc_hd__ebufn_8)
/grid_io_bottom_4_top_width_0_height_0_subtile_0__pin_inpad_0_ /Xsb_3__0_(sb_1__0_)/Xinput31(sky130_fd_sc_hd__buf_1)
/grid_io_bottom_4_top_width_0_height_0_subtile_0__pin_inpad_0_ /Xsb_4__0_(sb_1__0_)/Xinput29(sky130_fd_sc_hd__clkbuf_1)
/grid_io_bottom_5__0_/gfpga_pad_GPIO_PAD /Xgrid_io_bottom_5__0_(grid_io_bottom)/X_7_(sky130_fd_sc_hd__ebufn_8)
/grid_io_bottom_5_top_width_0_height_0_subtile_0__pin_inpad_0_ /Xsb_2__0_(sb_1__0_)/Xinput31(sky130_fd_sc_hd__buf_1)
/grid_io_bottom_5_top_width_0_height_0_subtile_0__pin_inpad_0_ /Xsb_3__0_(sb_1__0_)/Xinput29(sky130_fd_sc_hd__clkbuf_1)
/grid_io_bottom_6__0_/gfpga_pad_GPIO_PAD /Xgrid_io_bottom_6__0_(grid_io_bottom)/X_7_(sky130_fd_sc_hd__ebufn_8)
/grid_io_bottom_6_top_width_0_height_0_subtile_0__pin_inpad_0_ /Xsb_1__0_(sb_1__0_)/Xinput31(sky130_fd_sc_hd__buf_1)
/grid_io_bottom_6_top_width_0_height_0_subtile_0__pin_inpad_0_ /Xsb_2__0_(sb_1__0_)/Xinput29(sky130_fd_sc_hd__clkbuf_1)
/grid_io_bottom_7_top_width_0_height_0_subtile_0__pin_inpad_0_ /Xsb_0__0_(sb_0__0_)/Xinput20(sky130_fd_sc_hd__clkbuf_1)
/grid_io_bottom_7_top_width_0_height_0_subtile_0__pin_inpad_0_ /Xsb_1__0_(sb_1__0_)/Xinput29(sky130_fd_sc_hd__clkbuf_1)
/grid_io_left_0__1_/gfpga_pad_GPIO_PAD /Xgrid_io_left_0__1_(grid_io_left)/X_7_(sky130_fd_sc_hd__ebufn_8)
/grid_io_left_0__2_/gfpga_pad_GPIO_PAD /Xgrid_io_left_0__2_(grid_io_left)/X_7_(sky130_fd_sc_hd__ebufn_8)
/grid_io_left_0__3_/gfpga_pad_GPIO_PAD /Xgrid_io_left_0__3_(grid_io_left)/X_7_(sky130_fd_sc_hd__ebufn_8)
/grid_io_left_0_right_width_0_height_0_subtile_0__pin_inpad_0_ /Xsb_0__0_(sb_0__0_)/Xinput22(sky130_fd_sc_hd__clkbuf_1)
/grid_io_left_0_right_width_0_height_0_subtile_0__pin_inpad_0_ /Xsb_0__1_(sb_0__1_)/Xinput1(sky130_fd_sc_hd__clkbuf_1)
/grid_io_left_1_right_width_0_height_0_subtile_0__pin_inpad_0_ /Xsb_0__1_(sb_0__1_)/Xinput33(sky130_fd_sc_hd__clkbuf_1)
/grid_io_left_1_right_width_0_height_0_subtile_0__pin_inpad_0_ /Xsb_0__2_(sb_0__1_)/Xinput1(sky130_fd_sc_hd__clkbuf_1)
/grid_io_left_2_right_width_0_height_0_subtile_0__pin_inpad_0_ /Xsb_0__2_(sb_0__1_)/Xinput33(sky130_fd_sc_hd__clkbuf_1)
/grid_io_left_2_right_width_0_height_0_subtile_0__pin_inpad_0_ /Xsb_0__3_(sb_0__1_)/Xinput1(sky130_fd_sc_hd__clkbuf_1)
/grid_io_left_3_right_width_0_height_0_subtile_0__pin_inpad_0_ /Xsb_0__3_(sb_0__1_)/Xinput33(sky130_fd_sc_hd__clkbuf_1)
/grid_io_left_3_right_width_0_height_0_subtile_0__pin_inpad_0_ /Xsb_0__4_(sb_0__1_)/Xinput1(sky130_fd_sc_hd__clkbuf_1)
/grid_io_left_4_right_width_0_height_0_subtile_0__pin_inpad_0_ /Xsb_0__4_(sb_0__1_)/Xinput33(sky130_fd_sc_hd__clkbuf_1)
/grid_io_left_4_right_width_0_height_0_subtile_0__pin_inpad_0_ /Xsb_0__5_(sb_0__1_)/Xinput1(sky130_fd_sc_hd__clkbuf_1)
/grid_io_left_5_right_width_0_height_0_subtile_0__pin_inpad_0_ /Xsb_0__5_(sb_0__1_)/Xinput33(sky130_fd_sc_hd__clkbuf_1)
/grid_io_left_5_right_width_0_height_0_subtile_0__pin_inpad_0_ /Xsb_0__6_(sb_0__1_)/Xinput1(sky130_fd_sc_hd__clkbuf_1)
/grid_io_left_6_right_width_0_height_0_subtile_0__pin_inpad_0_ /Xsb_0__6_(sb_0__1_)/Xinput33(sky130_fd_sc_hd__clkbuf_1)
/grid_io_left_6_right_width_0_height_0_subtile_0__pin_inpad_0_ /Xsb_0__7_(sb_0__1_)/Xinput1(sky130_fd_sc_hd__clkbuf_1)
/grid_io_left_7_right_width_0_height_0_subtile_0__pin_inpad_0_ /Xsb_0__7_(sb_0__1_)/Xinput33(sky130_fd_sc_hd__clkbuf_1)
/grid_io_left_7_right_width_0_height_0_subtile_0__pin_inpad_0_ /Xsb_0__8_(sb_0__1_)/Xinput1(sky130_fd_sc_hd__clkbuf_1)
/grid_io_left_8_right_width_0_height_0_subtile_0__pin_inpad_0_ /Xsb_0__8_(sb_0__1_)/Xinput33(sky130_fd_sc_hd__clkbuf_1)
/grid_io_left_8_right_width_0_height_0_subtile_0__pin_inpad_0_ /Xsb_0__9_(sb_0__1_)/Xinput1(sky130_fd_sc_hd__clkbuf_1)
/grid_io_left_9_right_width_0_height_0_subtile_0__pin_inpad_0_ /Xsb_0__10_(sb_0__10_)/Xinput1(sky130_fd_sc_hd__clkbuf_1)
/grid_io_left_9_right_width_0_height_0_subtile_0__pin_inpad_0_ /Xsb_0__9_(sb_0__1_)/Xinput33(sky130_fd_sc_hd__clkbuf_1)
/grid_io_right_0_left_width_0_height_0_subtile_0__pin_inpad_0_ /Xsb_8__10_(sb_8__10_)/Xinput2(sky130_fd_sc_hd__clkbuf_1)
/grid_io_right_0_left_width_0_height_0_subtile_0__pin_inpad_0_ /Xsb_8__9_(sb_8__1_)/Xinput34(sky130_fd_sc_hd__clkbuf_1)
/grid_io_right_1_left_width_0_height_0_subtile_0__pin_inpad_0_ /Xsb_8__8_(sb_8__1_)/Xinput34(sky130_fd_sc_hd__clkbuf_1)
/grid_io_right_1_left_width_0_height_0_subtile_0__pin_inpad_0_ /Xsb_8__9_(sb_8__1_)/Xinput2(sky130_fd_sc_hd__buf_1)
/grid_io_right_2_left_width_0_height_0_subtile_0__pin_inpad_0_ /Xsb_8__7_(sb_8__1_)/Xinput34(sky130_fd_sc_hd__clkbuf_1)
/grid_io_right_2_left_width_0_height_0_subtile_0__pin_inpad_0_ /Xsb_8__8_(sb_8__1_)/Xinput2(sky130_fd_sc_hd__buf_1)
/grid_io_right_3_left_width_0_height_0_subtile_0__pin_inpad_0_ /Xsb_8__6_(sb_8__1_)/Xinput34(sky130_fd_sc_hd__clkbuf_1)
/grid_io_right_3_left_width_0_height_0_subtile_0__pin_inpad_0_ /Xsb_8__7_(sb_8__1_)/Xinput2(sky130_fd_sc_hd__buf_1)
/grid_io_right_4_left_width_0_height_0_subtile_0__pin_inpad_0_ /Xsb_8__5_(sb_8__1_)/Xinput34(sky130_fd_sc_hd__clkbuf_1)
/grid_io_right_4_left_width_0_height_0_subtile_0__pin_inpad_0_ /Xsb_8__6_(sb_8__1_)/Xinput2(sky130_fd_sc_hd__buf_1)
/grid_io_right_5_left_width_0_height_0_subtile_0__pin_inpad_0_ /Xsb_8__4_(sb_8__1_)/Xinput34(sky130_fd_sc_hd__clkbuf_1)
/grid_io_right_5_left_width_0_height_0_subtile_0__pin_inpad_0_ /Xsb_8__5_(sb_8__1_)/Xinput2(sky130_fd_sc_hd__buf_1)
/grid_io_right_6_left_width_0_height_0_subtile_0__pin_inpad_0_ /Xsb_8__3_(sb_8__1_)/Xinput34(sky130_fd_sc_hd__clkbuf_1)
/grid_io_right_6_left_width_0_height_0_subtile_0__pin_inpad_0_ /Xsb_8__4_(sb_8__1_)/Xinput2(sky130_fd_sc_hd__buf_1)
/grid_io_right_7_left_width_0_height_0_subtile_0__pin_inpad_0_ /Xsb_8__2_(sb_8__1_)/Xinput34(sky130_fd_sc_hd__clkbuf_1)
/grid_io_right_7_left_width_0_height_0_subtile_0__pin_inpad_0_ /Xsb_8__3_(sb_8__1_)/Xinput2(sky130_fd_sc_hd__buf_1)
/grid_io_right_8_left_width_0_height_0_subtile_0__pin_inpad_0_ /Xsb_8__1_(sb_8__1_)/Xinput34(sky130_fd_sc_hd__clkbuf_1)
/grid_io_right_8_left_width_0_height_0_subtile_0__pin_inpad_0_ /Xsb_8__2_(sb_8__1_)/Xinput2(sky130_fd_sc_hd__buf_1)
/grid_io_right_9_left_width_0_height_0_subtile_0__pin_inpad_0_ /Xsb_8__0_(sb_8__0_)/Xinput23(sky130_fd_sc_hd__clkbuf_1)
/grid_io_right_9_left_width_0_height_0_subtile_0__pin_inpad_0_ /Xsb_8__1_(sb_8__1_)/Xinput2(sky130_fd_sc_hd__buf_1)
/grid_io_top_0_bottom_width_0_height_0_subtile_0__pin_inpad_0_ /Xsb_0__10_(sb_0__10_)/Xinput23(sky130_fd_sc_hd__buf_1)
/grid_io_top_0_bottom_width_0_height_0_subtile_0__pin_inpad_0_ /Xsb_1__10_(sb_1__10_)/Xinput32(sky130_fd_sc_hd__buf_1)
/grid_io_top_1_bottom_width_0_height_0_subtile_0__pin_inpad_0_ /Xsb_1__10_(sb_1__10_)/Xinput34(sky130_fd_sc_hd__clkbuf_1)
/grid_io_top_1_bottom_width_0_height_0_subtile_0__pin_inpad_0_ /Xsb_2__10_(sb_1__10_)/Xinput32(sky130_fd_sc_hd__buf_1)
/grid_io_top_2_bottom_width_0_height_0_subtile_0__pin_inpad_0_ /Xsb_2__10_(sb_1__10_)/Xinput34(sky130_fd_sc_hd__clkbuf_1)
/grid_io_top_2_bottom_width_0_height_0_subtile_0__pin_inpad_0_ /Xsb_3__10_(sb_1__10_)/Xinput32(sky130_fd_sc_hd__buf_1)
/grid_io_top_3_bottom_width_0_height_0_subtile_0__pin_inpad_0_ /Xsb_3__10_(sb_1__10_)/Xinput34(sky130_fd_sc_hd__clkbuf_1)
/grid_io_top_3_bottom_width_0_height_0_subtile_0__pin_inpad_0_ /Xsb_4__10_(sb_1__10_)/Xinput32(sky130_fd_sc_hd__buf_1)
/grid_io_top_4_bottom_width_0_height_0_subtile_0__pin_inpad_0_ /Xsb_4__10_(sb_1__10_)/Xinput34(sky130_fd_sc_hd__clkbuf_1)
/grid_io_top_4_bottom_width_0_height_0_subtile_0__pin_inpad_0_ /Xsb_5__10_(sb_1__10_)/Xinput32(sky130_fd_sc_hd__buf_1)
/grid_io_top_5_bottom_width_0_height_0_subtile_0__pin_inpad_0_ /Xsb_5__10_(sb_1__10_)/Xinput34(sky130_fd_sc_hd__clkbuf_1)
/grid_io_top_5_bottom_width_0_height_0_subtile_0__pin_inpad_0_ /Xsb_6__10_(sb_1__10_)/Xinput32(sky130_fd_sc_hd__buf_1)
/grid_io_top_6_bottom_width_0_height_0_subtile_0__pin_inpad_0_ /Xsb_6__10_(sb_1__10_)/Xinput34(sky130_fd_sc_hd__clkbuf_1)
/grid_io_top_6_bottom_width_0_height_0_subtile_0__pin_inpad_0_ /Xsb_7__10_(sb_1__10_)/Xinput32(sky130_fd_sc_hd__buf_1)
/grid_io_top_7_bottom_width_0_height_0_subtile_0__pin_inpad_0_ /Xsb_7__10_(sb_1__10_)/Xinput34(sky130_fd_sc_hd__clkbuf_1)
/grid_io_top_7_bottom_width_0_height_0_subtile_0__pin_inpad_0_ /Xsb_8__10_(sb_8__10_)/Xinput23(sky130_fd_sc_hd__buf_1)
io_out[0] /Xgrid_io_bottom_7__0_(grid_io_bottom)/X_7_(sky130_fd_sc_hd__ebufn_8)
io_out[1] /Xgrid_io_bottom_8__0_(grid_io_bottom)/X_7_(sky130_fd_sc_hd__ebufn_8)
io_out[2] /Xgrid_io_right_9__1_(grid_io_right)/X_7_(sky130_fd_sc_hd__ebufn_8)
io_out[3] /Xgrid_io_right_9__2_(grid_io_right)/X_7_(sky130_fd_sc_hd__ebufn_8)
io_out[4] /Xgrid_io_right_9__3_(grid_io_right)/X_7_(sky130_fd_sc_hd__ebufn_8)
io_out[5] /Xgrid_io_right_9__4_(grid_io_right)/X_7_(sky130_fd_sc_hd__ebufn_8)
io_out[6] /Xgrid_io_right_9__5_(grid_io_right)/X_7_(sky130_fd_sc_hd__ebufn_8)
io_out[9] /Xgrid_io_right_9__6_(grid_io_right)/X_7_(sky130_fd_sc_hd__ebufn_8)
io_out[10] /Xgrid_io_right_9__7_(grid_io_right)/X_7_(sky130_fd_sc_hd__ebufn_8)
io_out[11] /Xgrid_io_right_9__8_(grid_io_right)/X_7_(sky130_fd_sc_hd__ebufn_8)
io_out[12] /Xgrid_io_right_9__9_(grid_io_right)/X_7_(sky130_fd_sc_hd__ebufn_8)
io_out[13] /Xgrid_io_right_9__10_(grid_io_right)/X_7_(sky130_fd_sc_hd__ebufn_8)
io_out[14] /Xgrid_io_top_8__11_(grid_io_top)/X_7_(sky130_fd_sc_hd__ebufn_8)
io_out[15] /Xgrid_io_top_7__11_(grid_io_top)/X_7_(sky130_fd_sc_hd__ebufn_8)
io_out[16] /Xgrid_io_top_6__11_(grid_io_top)/X_7_(sky130_fd_sc_hd__ebufn_8)
io_out[17] /Xgrid_io_top_5__11_(grid_io_top)/X_7_(sky130_fd_sc_hd__ebufn_8)
io_out[18] /Xgrid_io_top_4__11_(grid_io_top)/X_7_(sky130_fd_sc_hd__ebufn_8)
e
Hi @Mitch Bailey With your help I have fixed the warning in the oeb check and the LVS mismatch, with that the precheck has passed. But in the precheck I still get the following message 
WARNING ERC CHECK FAILED, stat=4
. Additionally i'm worry about the 
max fanout violations warning
How can i solved the ERC warning?, how can i fix the max fanout warning? and Does that affects the functionality of the system?
Precheck_22_FEB_2024___22_48_41.zip21-rcx_sta.checks.rpt
m
@Emilio Baungarten Sorry for the delay. I missed your reply. You might have to explicitly list your verilog files because 
verilog/gl
contains both the 
*.v
and 
*.nl.v
versions and they are both selected with the current globbing.
Copy code
SOURCE FILE(S): /home/baungarten2/Desktop/Caravel_FPGA/dependencies/pdks/sky130A/libs.ref/sky130_fd_sc_hd/spice/sky130_ef_sc_hd__decap_12.spice
 /home/baungarten2/Desktop/Caravel_FPGA/dependencies/pdks/sky130A/libs.ref/sky130_fd_sc_hd/spice/sky130_fd_sc_hd.spice
 /home/baungarten2/Desktop/Caravel_FPGA/verilog/gl/cbx_1__0_.nl.v
 /home/baungarten2/Desktop/Caravel_FPGA/verilog/gl/cbx_1__0_.v
 /home/baungarten2/Desktop/Caravel_FPGA/verilog/gl/cbx_1__10_.nl.v
 /home/baungarten2/Desktop/Caravel_FPGA/verilog/gl/cbx_1__10_.v
 /home/baungarten2/Desktop/Caravel_FPGA/verilog/gl/cbx_1__1_.nl.v
 /home/baungarten2/Desktop/Caravel_FPGA/verilog/gl/cbx_1__1_.v
 /home/baungarten2/Desktop/Caravel_FPGA/verilog/gl/cby_0__1_.nl.v
 /home/baungarten2/Desktop/Caravel_FPGA/verilog/gl/cby_0__1_.v
 /home/baungarten2/Desktop/Caravel_FPGA/verilog/gl/cby_1__1_.nl.v
 /home/baungarten2/Desktop/Caravel_FPGA/verilog/gl/cby_1__1_.v
 /home/baungarten2/Desktop/Caravel_FPGA/verilog/gl/cby_8__1_.nl.v
 /home/baungarten2/Desktop/Caravel_FPGA/verilog/gl/cby_8__1_.v
 /home/baungarten2/Desktop/Caravel_FPGA/verilog/gl/grid_clb.nl.v
 /home/baungarten2/Desktop/Caravel_FPGA/verilog/gl/grid_clb.v
Looks like you still have the undriven inputs (98) from the CVC check and fanout and slew errors due to non-synthesis of the top level.
e
Hi @Mitch Bailey, sorry for the delay, i have been tried multiples things, i did the synthesis at the top level, with that and changing the FANOUT to 16 i solved the fanout and slew warnings, nevertheless, the 
WARNING ERC CHECK FAILED, stat=4
still happens, even after changing 
*.v
and 
*.nl.v
I attached the last precheck.
28_FEB_2024___02_39_58.zip
m
Excellent progress! No LVS, fanout/slew errors. CVC(RV) errors have dropped from 196(98) to 160(80). The net names shown are the extracted nets, which might differ from the verilog net names.
Copy code
/gfpga_pad_GPIO_PAD\[3\] /Xgrid_io_top_4__11_(grid_io_top)/X_7_(sky130_fd_sc_hd__ebufn_8)
/gfpga_pad_GPIO_PAD\[3\] /Xwire4878(sky130_fd_sc_hd__clkbuf_2)
/gfpga_pad_GPIO_PAD\[4\] /Xgrid_io_top_5__11_(grid_io_top)/X_7_(sky130_fd_sc_hd__ebufn_8)
/gfpga_pad_GPIO_PAD\[4\] /Xwire4872(sky130_fd_sc_hd__clkbuf_2)
/gfpga_pad_GPIO_PAD\[5\] /Xgrid_io_top_6__11_(grid_io_top)/X_7_(sky130_fd_sc_hd__ebufn_8)
/gfpga_pad_GPIO_PAD\[5\] /Xwire4866(sky130_fd_sc_hd__clkbuf_2)
/gfpga_pad_GPIO_PAD\[6\] /Xgrid_io_top_7__11_(grid_io_top)/X_7_(sky130_fd_sc_hd__ebufn_8)
/gfpga_pad_GPIO_PAD\[6\] /Xwire4860(sky130_fd_sc_hd__clkbuf_2)
/gfpga_pad_GPIO_PAD\[7\] /Xgrid_io_top_8__11_(grid_io_top)/X_7_(sky130_fd_sc_hd__ebufn_8)
/gfpga_pad_GPIO_PAD\[7\] /Xwire4849(sky130_fd_sc_hd__clkbuf_2)
/gfpga_pad_GPIO_PAD\[8\] /Xgrid_io_right_9__10_(grid_io_right)/X_7_(sky130_fd_sc_hd__ebufn_8)
/gfpga_pad_GPIO_PAD\[8\] /Xwire4963(sky130_fd_sc_hd__clkbuf_2)
/gfpga_pad_GPIO_PAD\[9\] /Xgrid_io_right_9__9_(grid_io_right)/X_7_(sky130_fd_sc_hd__ebufn_8)
/gfpga_pad_GPIO_PAD\[9\] /Xwire4908(sky130_fd_sc_hd__dlymetal6s2s_1)
/gfpga_pad_GPIO_PAD\[10\] /Xgrid_io_right_9__8_(grid_io_right)/X_7_(sky130_fd_sc_hd__ebufn_8)
/gfpga_pad_GPIO_PAD\[10\] /Xwire4913(sky130_fd_sc_hd__clkbuf_2)
/gfpga_pad_GPIO_PAD\[11\] /Xgrid_io_right_9__7_(grid_io_right)/X_7_(sky130_fd_sc_hd__ebufn_8)
/gfpga_pad_GPIO_PAD\[11\] /Xwire4917(sky130_fd_sc_hd__clkbuf_2)
/gfpga_pad_GPIO_PAD\[12\] /Xgrid_io_right_9__6_(grid_io_right)/X_7_(sky130_fd_sc_hd__ebufn_8)
/gfpga_pad_GPIO_PAD\[12\] /Xwire4921(sky130_fd_sc_hd__clkbuf_2)
/gfpga_pad_GPIO_PAD\[13\] /Xgrid_io_right_9__5_(grid_io_right)/X_7_(sky130_fd_sc_hd__ebufn_8)
/gfpga_pad_GPIO_PAD\[13\] /Xwire4925(sky130_fd_sc_hd__clkbuf_2)
/gfpga_pad_GPIO_PAD\[14\] /Xgrid_io_right_9__4_(grid_io_right)/X_7_(sky130_fd_sc_hd__ebufn_8)
/gfpga_pad_GPIO_PAD\[14\] /Xwire4929(sky130_fd_sc_hd__clkbuf_2)
/gfpga_pad_GPIO_PAD\[15\] /Xgrid_io_right_9__3_(grid_io_right)/X_7_(sky130_fd_sc_hd__ebufn_8)
/gfpga_pad_GPIO_PAD\[15\] /Xwire4937(sky130_fd_sc_hd__clkbuf_2)
/gfpga_pad_GPIO_PAD\[16\] /Xgrid_io_right_9__2_(grid_io_right)/X_7_(sky130_fd_sc_hd__ebufn_8)
/gfpga_pad_GPIO_PAD\[16\] /Xwire4945(sky130_fd_sc_hd__clkbuf_2)
/gfpga_pad_GPIO_PAD\[17\] /Xgrid_io_right_9__1_(grid_io_right)/X_7_(sky130_fd_sc_hd__ebufn_8)
/gfpga_pad_GPIO_PAD\[17\] /Xwire4953(sky130_fd_sc_hd__clkbuf_2)
/gfpga_pad_GPIO_PAD\[18\] /Xgrid_io_bottom_8__0_(grid_io_bottom)/X_7_(sky130_fd_sc_hd__ebufn_8)
/gfpga_pad_GPIO_PAD\[18\] /Xwire5053(sky130_fd_sc_hd__clkbuf_2)
/gfpga_pad_GPIO_PAD\[19\] /Xgrid_io_bottom_7__0_(grid_io_bottom)/X_7_(sky130_fd_sc_hd__ebufn_8)
/gfpga_pad_GPIO_PAD\[19\] /Xwire5068(sky130_fd_sc_hd__dlymetal6s2s_1)
/grid_io_bottom_0_top_width_0_height_0_subtile_0__pin_inpad_0_ /Xmax_length5045(sky130_fd_sc_hd__buf_1)
/grid_io_bottom_0_top_width_0_height_0_subtile_0__pin_inpad_0_ /Xwire5044(sky130_fd_sc_hd__buf_1)
/grid_io_bottom_1__0_/gfpga_pad_GPIO_PAD /Xgrid_io_bottom_1__0_(grid_io_bottom)/X_7_(sky130_fd_sc_hd__ebufn_8)
/grid_io_bottom_1_top_width_0_height_0_subtile_0__pin_inpad_0_ /Xwire5060(sky130_fd_sc_hd__clkbuf_2)
/grid_io_bottom_2__0_/gfpga_pad_GPIO_PAD /Xgrid_io_bottom_2__0_(grid_io_bottom)/X_7_(sky130_fd_sc_hd__ebufn_8)
/grid_io_bottom_2_top_width_0_height_0_subtile_0__pin_inpad_0_ /Xwire5073(sky130_fd_sc_hd__clkbuf_2)
/grid_io_bottom_3__0_/gfpga_pad_GPIO_PAD /Xgrid_io_bottom_3__0_(grid_io_bottom)/X_7_(sky130_fd_sc_hd__ebufn_8)
/grid_io_bottom_3_top_width_0_height_0_subtile_0__pin_inpad_0_ /Xwire5078(sky130_fd_sc_hd__clkbuf_2)
/grid_io_bottom_4__0_/gfpga_pad_GPIO_PAD /Xgrid_io_bottom_4__0_(grid_io_bottom)/X_7_(sky130_fd_sc_hd__ebufn_8)
/grid_io_bottom_4_top_width_0_height_0_subtile_0__pin_inpad_0_ /Xwire5083(sky130_fd_sc_hd__clkbuf_2)
/grid_io_bottom_5__0_/gfpga_pad_GPIO_PAD /Xgrid_io_bottom_5__0_(grid_io_bottom)/X_7_(sky130_fd_sc_hd__ebufn_8)
/grid_io_bottom_5_top_width_0_height_0_subtile_0__pin_inpad_0_ /Xwire5088(sky130_fd_sc_hd__clkbuf_2)
/grid_io_bottom_6__0_/gfpga_pad_GPIO_PAD /Xgrid_io_bottom_6__0_(grid_io_bottom)/X_7_(sky130_fd_sc_hd__ebufn_8)
/grid_io_bottom_6_top_width_0_height_0_subtile_0__pin_inpad_0_ /Xwire5093(sky130_fd_sc_hd__clkbuf_2)
/grid_io_bottom_7_top_width_0_height_0_subtile_0__pin_inpad_0_ /Xwire5097(sky130_fd_sc_hd__clkbuf_2)
/grid_io_left_0__1_/gfpga_pad_GPIO_PAD /Xgrid_io_left_0__1_(grid_io_left)/X_7_(sky130_fd_sc_hd__ebufn_8)
/grid_io_left_0__2_/gfpga_pad_GPIO_PAD /Xgrid_io_left_0__2_(grid_io_left)/X_7_(sky130_fd_sc_hd__ebufn_8)
/grid_io_left_0__3_/gfpga_pad_GPIO_PAD /Xgrid_io_left_0__3_(grid_io_left)/X_7_(sky130_fd_sc_hd__ebufn_8)
/grid_io_left_0_right_width_0_height_0_subtile_0__pin_inpad_0_ /Xwire5030(sky130_fd_sc_hd__clkbuf_2)
/grid_io_left_1_right_width_0_height_0_subtile_0__pin_inpad_0_ /Xwire5023(sky130_fd_sc_hd__clkbuf_2)
/grid_io_left_2_right_width_0_height_0_subtile_0__pin_inpad_0_ /Xwire5015(sky130_fd_sc_hd__clkbuf_2)
/grid_io_left_3_right_width_0_height_0_subtile_0__pin_inpad_0_ /Xwire5007(sky130_fd_sc_hd__clkbuf_2)
/grid_io_left_4_right_width_0_height_0_subtile_0__pin_inpad_0_ /Xwire4999(sky130_fd_sc_hd__clkbuf_2)
/grid_io_left_5_right_width_0_height_0_subtile_0__pin_inpad_0_ /Xwire4991(sky130_fd_sc_hd__clkbuf_2)
/grid_io_left_6_right_width_0_height_0_subtile_0__pin_inpad_0_ /Xwire4983(sky130_fd_sc_hd__clkbuf_2)
/grid_io_left_7_right_width_0_height_0_subtile_0__pin_inpad_0_ /Xwire4975(sky130_fd_sc_hd__clkbuf_2)
/grid_io_left_8_right_width_0_height_0_subtile_0__pin_inpad_0_ /Xwire4967(sky130_fd_sc_hd__clkbuf_2)
/grid_io_left_9_right_width_0_height_0_subtile_0__pin_inpad_0_ /Xwire5038(sky130_fd_sc_hd__clkbuf_2)
/grid_io_right_0_left_width_0_height_0_subtile_0__pin_inpad_0_ /Xwire4956(sky130_fd_sc_hd__clkbuf_2)
/grid_io_right_1_left_width_0_height_0_subtile_0__pin_inpad_0_ /Xwire4902(sky130_fd_sc_hd__clkbuf_2)
/grid_io_right_2_left_width_0_height_0_subtile_0__pin_inpad_0_ /Xwire4911(sky130_fd_sc_hd__clkbuf_2)
/grid_io_right_3_left_width_0_height_0_subtile_0__pin_inpad_0_ /Xwire4916(sky130_fd_sc_hd__clkbuf_2)
/grid_io_right_4_left_width_0_height_0_subtile_0__pin_inpad_0_ /Xwire4920(sky130_fd_sc_hd__clkbuf_2)
/grid_io_right_5_left_width_0_height_0_subtile_0__pin_inpad_0_ /Xwire4924(sky130_fd_sc_hd__clkbuf_2)
/grid_io_right_6_left_width_0_height_0_subtile_0__pin_inpad_0_ /Xwire4928(sky130_fd_sc_hd__clkbuf_2)
/grid_io_right_7_left_width_0_height_0_subtile_0__pin_inpad_0_ /Xwire4932(sky130_fd_sc_hd__clkbuf_2)
/grid_io_right_8_left_width_0_height_0_subtile_0__pin_inpad_0_ /Xwire4940(sky130_fd_sc_hd__clkbuf_2)
/grid_io_right_9_left_width_0_height_0_subtile_0__pin_inpad_0_ /Xwire4947(sky130_fd_sc_hd__clkbuf_2)
/grid_io_top_0_bottom_width_0_height_0_subtile_0__pin_inpad_0_ /Xwire4900(sky130_fd_sc_hd__buf_2)
/grid_io_top_1_bottom_width_0_height_0_subtile_0__pin_inpad_0_ /Xwire4893(sky130_fd_sc_hd__clkbuf_2)
/grid_io_top_2_bottom_width_0_height_0_subtile_0__pin_inpad_0_ /Xwire4888(sky130_fd_sc_hd__clkbuf_2)
/grid_io_top_3_bottom_width_0_height_0_subtile_0__pin_inpad_0_ /Xwire4883(sky130_fd_sc_hd__clkbuf_2)
/grid_io_top_4_bottom_width_0_height_0_subtile_0__pin_inpad_0_ /Xwire4877(sky130_fd_sc_hd__clkbuf_2)
/grid_io_top_5_bottom_width_0_height_0_subtile_0__pin_inpad_0_ /Xwire4871(sky130_fd_sc_hd__clkbuf_2)
/grid_io_top_6_bottom_width_0_height_0_subtile_0__pin_inpad_0_ /Xwire4865(sky130_fd_sc_hd__clkbuf_2)
/grid_io_top_7_bottom_width_0_height_0_subtile_0__pin_inpad_0_ /Xwire4853(sky130_fd_sc_hd__buf_2)
If these are intentionally tristate signals at the top level, then you might need to specify them as signals that should not be buffered. I’m not exactly sure how to do that.
You might need to adjust the drive strength in the macros to meet your timing requirements.
e
Hi @Mitch Bailey, and sorry i got busy last days. The signals Hi-Z comes from the GPIO ports, the GPIO module is the following:
Copy code
module GPIO (
  input A, // Data output
  output Y, // Data input
  inout PAD, // bi-directional pad
  input DIR // direction control
);
  //----- when direction enabled, the signal is propagated from PAD to data input
  assign Y = DIR ? PAD : 1'bz;
  //----- when direction is disabled, the signal is propagated from data out to pad
  assign PAD = DIR ? 1'bz : A;
endmodule
After layout process the generated GL code is the following:
Copy code
module grid_io_bottom(prog_clk, gfpga_pad_GPIO_PAD, top_width_0_height_0_subtile_0__pin_outpad_0_, ccff_head, top_width_0_height_0_subtile_0__pin_inpad_0_, ccff_tail);
  wire _0_;
  wire _1_;
  wire _2_;
  input ccff_head;
  wire ccff_head;
  output ccff_tail;
  wire ccff_tail;
  inout gfpga_pad_GPIO_PAD;
  wire gfpga_pad_GPIO_PAD;
  input prog_clk;
  wire prog_clk;
  output top_width_0_height_0_subtile_0__pin_inpad_0_;
  wire top_width_0_height_0_subtile_0__pin_inpad_0_;
  input top_width_0_height_0_subtile_0__pin_outpad_0_;
  wire top_width_0_height_0_subtile_0__pin_outpad_0_;
  sky130_fd_sc_hd__buf_6 _3_ (
    .A(ccff_tail),
    .X(_0_)
  );
  sky130_fd_sc_hd__buf_6 _4_ (
    .A(_0_),
    .X(_2_)
  );
  sky130_fd_sc_hd__inv_2 _5_ (
    .A(ccff_tail),
    .Y(_1_)
  );
  sky130_fd_sc_hd__dfxtp_2 _6_ (
    .CLK(prog_clk),
    .D(ccff_head),
    .Q(ccff_tail)
  );
  sky130_fd_sc_hd__ebufn_2 _7_ (
    .A(gfpga_pad_GPIO_PAD),
    .TE_B(_1_),
    .Z(top_width_0_height_0_subtile_0__pin_inpad_0_)
  );
  sky130_fd_sc_hd__ebufn_2 _8_ (
    .A(top_width_0_height_0_subtile_0__pin_outpad_0_),
    .TE_B(_2_),
    .Z(gfpga_pad_GPIO_PAD)
  );
endmodule
The 
sky130_fd_sc_hd__ebufn_2
cell is a tri-state buffer and the TE_B is the buffer enable the wire 
_1_
come from a inverter so the tri-state buffer 
_7_
will not be activated at the same time as buffer tri-state buffer 
_8_
. Is it OK or can it create a problem?
m
Does 
gfpga_pad_GPIO_PAD
connect directly to the 
user_project_wrapper
io_in
or 
io_out
ports? It appears that the GPIO block is switching between using 
gpio_pad_GPIO_PAD
as input or output. When 
ccff_tail
is high, what drives 
top_width_0_height_0_subtile_0__pin_inpad_0_
? When 
ccff_tail
is low, what drives 
gfpga_pad_GPIO_PAD
?
e
gfpga_pad_GPIO_PAD
is instantiated on multiples modules some modules are connected to 
io_in
and another to 
io_out
, but never at both. When 
ccff_tail
is high 
top_width_0_height_0_subtile_0__pin_inpad_0_
has the value of 
gfpga_pad_GPIO_PAD
when 
ccff_tail
is low 
gfpga_pad_GPIO_PAD
has the value of 
top_width_0_height_0_subtile_0__pin_outpad_0_
.
m
@Emilio Baungarten You’re right; I drew the schematic wrong. What I really want to know is when 
ccff_tail
is high, what drives 
gfpga_pad_GPIO_PAD
and when 
ccff_tail
is low, what drives 
top_width_0_height_0_subtile_0__pin_inpad_0_
?
e
For those condition both manage `1'bz`; When 
ccff_tail
is high, the instance 
sky130_fd_sc_hd__ebufn_2 _8_
receive a `1'b1`in the port 
TE_B
that cell contain a 
bufif0
so the output is`1'bz`,on the other hand, when 
ccff_tail
is low the instance 
sky130_fd_sc_hd__ebufn_2 _7_
have 
1'b1
in the port 
TE_B
due to the inverter an the output is 
1'bz
. Here is the verilog file of the 
sky130_fd_sc_hd__ebufn_2
cell:
Copy code
/ Import user defined primitives.

`celldefine
module sky130_fd_sc_hd__ebufn_2 (
    Z   ,
    A   ,
    TE_B,
    VPWR,
    VGND,
    VPB ,
    VNB
);

    // Module ports
    output Z   ;
    input  A   ;
    input  TE_B;
    input  VPWR;
    input  VGND;
    input  VPB ;
    input  VNB ;

    // Local signals
    wire pwrgood_pp0_out_A  ;
    wire pwrgood_pp1_out_teb;

    //                                 Name         Output               Other arguments
    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_A  , A, VPWR, VGND                         );
    sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_teb, TE_B, VPWR, VGND                      );
    bufif0                             bufif00     (Z                  , pwrgood_pp0_out_A, pwrgood_pp1_out_teb);

endmodule
`endcelldefine
m
So both will be in a 
1'bz
state. The problem is that hi-z signals should not be buffered and the signals previously listed are buffered.
8 Views
Open in Slack
PreviousNext
Powered by