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Hello, I encountered an LVS error. It seems the e...
# lvs
y
Hello, I encountered an LVS error. It seems the error is related to mismatched pin names of MOSFETs. Done anyone know how to solve it?
m
@Yusuke Sakemi I suspect that your source spice netlist has transistors as ‘M’ devices. They should be ‘X’ devices to match the layout. If you share your extracted spice netlist and the spice netlist output of xschem, I can give you a better answer.
y
Thanks for reply! These are the spice codes (top: xschem spice, bottom: magic).
m
@Yusuke Sakemi the netlist generated from the schematic has ‘M’ devices. They should be ‘X’ devices as in the layout extracted version. Are you using xschem? If so, make sure the 
Simulation
-> 
LVS
-> 
Use 'spiceprefix' attribute
is checked.
m
what does that do Mitch? What are X and M devices?
m
In the standard sky130A library, a device in xschem may have the following properties
Copy code
name=M11
L=0.8
W=16
nf=8
mult=1
ad="'int((nf+1)/2) * W/nf * 0.29'" 
pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
as="'int((nf+2)/2) * W/nf * 0.29'" 
ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
nrd="'0.29 / W'" nrs="'0.29 / W'"
sa=0 sb=0 sd=0
model=pfet_g5v0d10v5
spiceprefix=X
The symbol master has the following parameters
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type=pmos
lvs_format="@spiceprefix@name @pinlist sky130_fd_pr__@model L=@L W=@W nf=@nf m=@mult"
format="@spiceprefix@name @pinlist sky130_fd_pr__@model L=@L W=@W
+ nf=@nf ad=@ad as=@as pd=@pd ps=@ps
+ nrd=@nrd nrs=@nrs sa=@sa sb=@sb sd=@sd 
+ mult=@mult m=@mult"
template="name=M1
L=0.5
W=1
nf=1
mult=1
ad=\"'int((nf+1)/2) * W/nf * 0.29'\"
pd=\"'2*int((nf+1)/2) * (W/nf + 0.29)'\"
as=\"'int((nf+2)/2) * W/nf * 0.29'\" 
ps=\"'2*int((nf+2)/2) * (W/nf + 0.29)'\"
nrd=\"'0.29 / W'\" nrs=\"'0.29 / W'\"
sa=0 sb=0 sd=0
model=pfet_g5v0d10v5
spiceprefix=X
"
I believe the 
Simulation
-> 
LVS
-> 
Use 'spiceprefix' attribute
selection enables the spiceprefix substitution. With 
spiceprefix
disabled, the device would be netlisted as
Copy code
M2 OUT IN VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=2 nf=1 m=5398
with 
spiceprefix
enabled, you get
Copy code
XM2 OUT IN VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=2 nf=1 m=5398
which will work with the current pdk simulation and LVS setups.
y
@Mitch Bailey Thanks for your support. LVS was successfully done when I convert M[1,2,3,4] into XM[1,2,3,4] manually. However, I encountered a wirerd situation in xschem when outputting a netlist. The devise is defined as XM[1,2,3,4] when LVS .subckt is ON (botton in the figure). While, the device is defined as M[1,2,3,4] when LVS .subckt is OFF (top in the figure). In bothe cases, spiceprefix is ON. Do you know why this happens?
t
b
layout_spice.png
schematic_spice.png
schematics.png
Layout.png
Hi, I am running some issue on LVS, there is two cells in my layout which are from the standard cell libraries are causing most of the mismatch in the LVS. can someone please look into the files I attached above and give me some recommendation based on screenshots I posted?
Thank you
comp.out.png
m
@Yusuke Sakemi Not sure why you’re getting different results with LVS subckt on. @Stefan Schippers?
@thedaileyrelish when you use standard cells in schematics, you need to provide the underlying circuit structure that is located in 
$PDK_ROOT/$PDK/libs.ref/sky130_fd_sc_hd/spicce/sky130_fd_sc_hd.spice
Try adding this as and include statement in your schematic.
s
@Yusuke Sakemi (@Mitch Bailey) please provide the testbench schematic (.sch) and the .sym and .sch of the subcircuits, so I can do a test.
@Yusuke Sakemi (@Mitch Bailey) the problem happens if the transistor symbol has a 
lvs_format
attribute in addition to the standard 
format
attribute. If such an attribute exists and LVS netlist is enabled it will be used instead of 
format
. If you check the symbol and edit its attributes you will probably see that 
lvs_format
does not have 
@spiceprefix
placed before 
@name
However this was fixed in Jan 3 2023:
Copy code
commit e5e0ff5c76732ae899d2b96bf556523118a3982b
Author: stefan schippers <stefan.schippers@gmail.com>
Date:   Tue Jan 3 14:27:01 2023 +0100

    added @spiceprefix before @name in lvs_netlist attributes. @spicepfefix can be disabled with Simulation->Use spiceprefix attribute
👍 2
t
Mitch Bailey, what do you mean provide "$PDK_ROOT/$PDK/libs.ref/sky130_fd_sc_hd/spicce/sky130_fd_sc_hd.spice"? do mean include this drive into one of my spice files? and if so which one I should include?
m
right. There was a typo in the path, but fixed now. You can either modify the netlist manually or I think you can add a 
code
symbol from the device library. This may not be the best solution for a full chip integration, but it should work in your case.
s
I think @Harald Pretl will have the answer for this. May be there are some specific commands to update the docker image, so before doing manual work like copying files let'se see his advice.
y
@Stefan Schippers Thanks for your reply. Sorry, I am using IIC-OSIC, which is not a docker image and the name has been changed as osic-multitools now. @Harald Pretl Is there a recommended way of updating osic-multitools and/or updating a specific software such as xschem?
s
@Yusuke Sakemi Looking into the 
osic-multitools
it looks to me that running 
iic-osic-setup.sh
again will do an update: see the relevant portion of the script for xschem:
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# Install/update xschem
# ---------------------
if [ ! -d "$SRC_DIR/xschem" ]; then
	echo ">>>> Installing xschem"
	sudo apt build-dep -y xschem
	git clone <https://github.com/StefanSchippers/xschem.git> "$SRC_DIR/xschem"
	cd "$SRC_DIR/xschem" || exit
	./configure
else
	echo ">>>> Updating xschem"
	cd "$SRC_DIR/xschem" || exit
	git pull
fi
make -j"$(nproc)" && sudo make install
so if the src/xschem directory is already present it will update (git pull) and rebuild.
y
Thank you very much, Stefan! I am gonna try to update following your suggestion.
t
comp.out1.png
schematicspice.png
Layoutspice.png
Hi Mitch Bailey, I am encountering some problem on magic LVS. I attached the comp.out generated file where it say top level cell failed pin matching. Those pins show up on both of my spice files but when I run the LVS it never happen to compare those I/O pins ( VDD, VSS, CLK, UPDOWN, Vmac and Vref). Any recommendations or tips please? Thank you in advance!
m
Try netlisting your schematic for LVS. 
Simulation
-> 
LVS
-> 
LVS netlist: top level is a .subckt:
t
Layoutspice1.png
schematicspice1.png
Screenshot from 2024-03-07 11-49-06.png
Hi Mitch Bailey, Thank you for the helpful tips. I enabled the LVS netlist of the schematics but unfortunately that didn't solve my problem. My LVS didn't comparing the top cell pins plus it now say the cell layout.spice has no elements. I attached both of my spice files above this writing and a screenshot of the comp.out file. Could you please look into the files and give a further advise on how to tackle this bug? I really appreciate your input and volunteer help on this project.
Thank you in advance.
m
Your schematic netlist is not being output as an LVS netlist. The top level subckt is commented out along with the pin definitions. Make sure the option is checked before netlisting.
t
screenspice.png
when I enabled the LVS netlist, this is what the generated spice looks like the above screen and I think it is missing information that suppose to be there and LVS comp.out file has no result as shown below.
LVS result.png
LVSnetlist_enabled.png
m
You’ve shared 
comp_layout.spice
but the 
comp.out
results show 
comp_layout1.spice
. Can you share 
comp_layout1.spice
?
t
comp_layout1.spice
comp_layout1.spice
Yes, I attached it here as a spice.
m
What netgen command are you using for comparison? The layout and schematic block names are different.
t
netgen -batch lvs "8bitadc_comp.spice" "comp_layout1.spice" /home/ece393/open_pdks/share/pdk/sky130A/libs.tech/netgen/sky130A_setup.tcl
I am using this command.
what block names are different? do your mean the spice file names are different?
m
Try
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netgen -batch lvs "comp_layout1.spice comp_layout"  "8bitadc_comp.spice 8bitadc_comp" /home/ece393/open_pdks/share/pdk/sky130A/libs.tech/netgen/sky130A_setup.tcl
Although either order is technically ok, having the layout first matches other flows. You’ll want to specify the top cellnames if they don’t match.
t
comp.out
comp.out
When run spice files along with other files it made more worse plus the number of mismatches have increased.
How should I specify the top cellnames? what do you mean specify?
thank you
*Thank you.
m
You’re on the right track!
Copy code
Subcircuit summary:
Circuit 1: comp_layout                     |Circuit 2: 8bitadc_comp
-------------------------------------------|-------------------------------------------
sky130_fd_pr__nfet_01v8 (5)                |sky130_fd_pr__nfet_01v8 (5)
sky130_fd_pr__pfet_01v8 (6)                |sky130_fd_pr__pfet_01v8 (6)
c (98)                                     |(no matching element)
sky130_fd_sc_hd__buf_1 (1)                 |sky130_fd_sc_hd__buf_1 (1)
sky130_fd_sc_hd__inv_1 (1)                 |sky130_fd_sc_hd__inv_1 (1)
$ (1)                                      |(no matching element)
Number of devices: 112 **Mismatch**        |Number of devices: 13 **Mismatch**
Number of nets: 16 **Mismatch**            |Number of nets: 14 **Mismatch**
---------------------------------------------------------------------------------------
You can see that the layout has capacitors and some other strange device that’s not in the schematic. What commands are you using to create the extracted netlist for LVS? I use
Copy code
extract no all
extract do aliases
extract do local
extract style ngspice()
extract

ext2spice lvs
t
I am using these commands,
extract all
ext2spice
Thank you Mitch Bailey, I will try implementing your suggested commands and I will get back to you what I found.
👍 1
Hi Mitch, I try extracting layout file using the commands you shared but unfortunately that didn't solve my problem of top level cell pins.
also question, on xschem if I try to generate spice file from schematics I can see the netlist spice is being generated and I hit save but it never saves the file into my computer. Do you know how to remedy this problem?
s
What are you exactly doing? Where are you clicking Save ? netlists are by default saved in 
~/.xschem/simulations
, unless you change the default location.
m
unfortunately that solve my problem of top level cell pins.
Not sure what you mean. Could you share your extraction commands and the extracted spice file?
t
missingMOSes.png
can anyone advise with me on how to solve when this happens where all the transistors somehow disappear?
I am using an open source tapeout project which has been done by people previously.
s
you need to copy the file 
.../pdk/sky130A/libs.tech/xschem/xschemrc
in the directory from where you start xschem. Also set 
PDK_ROOT
and 
PDK
environment variables if your open_pdks installation is not in 
~/share/pdk
or 
/usr/local/share/pdk
. For more details see this page.
m
If Stefan’s suggestion doesn’t work, try selecting a missing instance and type 
q
to get the properties. Make sure the device path is relative and not absolute.
👍 1
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