@Mitch Bailey, I have a question related to the schematic netlist streamed out from the xschem. There are 2 different formats defined in the symbol

lvs_format="@name @pinlist @model L=@L W=@W ng=@ng m=@m"
format="@spiceprefix@name @pinlist @model W=@W L=@L ng=@ng m=@m"

Finally the lvs format does not have the spice prefix. What is the reason to implement it this way? I am asking because we (IHP) are pushing for Qucs-S to be the principal schematic capture tool in RF flow and we would like to generate netlists using valid format. Regards

@Krzysztof Herman In some cases the netlist line for the simulator is different than the netlist line to be used to compare with the layout extracted netlist. In these cases a

lvs_format

attribute is used. xschem has an option '`LVS netlist`'. When this option is enabled the netlist rule for a component is taken from the

lvs_format

attribute if existing (otherwise use the standard

format

attribute). A typical case is for example a silicon diode that is described in the spice models as a subcircuit (so an X is needed in front of the instance name),

XDxxx

while for LVS it is treated as a normal diode,

Dxxx

line). Another scenario where this

lvs_format

may be used is for components that have a lot of instance parameters to describe simulation device details, while for checking schematic vs layout only the physical dimension parameters and multiplier are used (like

W

,

L

,

m

for MOS transistors). To avoid warnings from the LVS compare tool (like Netgen) about unrecognized parameters a dedicated

lvs_format

netlist rule can be used. Of course the ideal situation is to avoid these simulation-LVS differences so no

lvs_format

is needed at all...

@Stefan Schippers thank you for the answer. So in fact the rule of thumb is to generate both netlists using the same device names not to confuse LVS tool. In IHP flow LVS will be held by Klayout and I do not even know if you can access (stream out) the layout extracted netlist, do you ? Maybe @Amro Tork does? Regards

@Krzysztof Herman some Layout vs schematic checks are done with an external tool, so this tool gets a connectivity netlist from the schematic tool and a connectivity netlist from the layout tool (magic, for example). The two netlists are then compared. Other tools (may be Klayout) have the LVS check integrated, so they probably just need the netlist from the schematic tool. But some other people will probably know the flow detail better and correct me if I mis-stated something and answer about the ability to get a spice netlist out of Klayout.

@Stefan Schippers thanx!. I know pretty well the xschem +magic + netgen flow for LVS. The major question for me how Klayout handles this internally of if you could stream it out and then used netgen to perform LVS check