Hi everyone,I am trying to design a simple inverter.But I M getting this error.When checked the log file in synthesis,it says that the network is combinational.

Hi! 'Network is combinational' may be logged as an error, but is not necessarily considered to be the error. The error I see is

Synthesis failed. Signal not matching port size. Search for 'Resizing cell port' in /home/engtech/...

-- I recall that this normally means you have instantiated a module, and at least one of the module's ports is expecting a given number of signals (e.g. in your case an inverter would likely have just a single input and a single output), but at the point of instantiation you have assigned more or fewer signals than the port is expecting. For example, if

io_in

is 38 signals wide, I think you would get this error if you did

.my_inverter_input(io_in)

and instead you might want to do

.my_inverter_input(io_in[10])

or whatever.