Hello, I have a problem generating the gds file, showing the following error. The error message states that the problem is with: WARNING GRT-0040] Net VDD has wires outside die area. [WARNING GRT-0040] Net VSS has wires outside die area My .json file { "PDK": "sky130A", "STD_CELL_LIBRARY": [ "sky130_fd_sc_hd" ], "DESIGN_NAME": "aps_top", "VERILOG_FILES":[ "dir::../../verilog/gl/aps_top.v" ], "VERILOG_FILES_BLACKBOX":[ "dir::macros/blackbox/decoder128.v", "dir::macros/blackbox/decoder.v" ], "EXTRA_LEFS":[ "dir::../../lef/decoder128.lef", "dir::../../lef/decoder.lef" ], "EXTRA_GDS_FILES":[ "dir::../../gds/decoder128.gds", "dir::../../gds/decoder.gds" ], "EXTRA_LIBS":[ ], "RUN_CTS": false, "CLOCK_PORT": null, "FP_SIZING": "absolute", "DIE_AREA":[0,0,3000,3000], "FP_PDN_VPITCH": 50, "FP_PDN_HPITCH": 50, "DESIGN_IS_CORE": true, "FP_PDN_CORE_RING":true, "MAGIC_EXT_USE_GDS": true, "RT_MAX_LAYER": "met4", "VDD_NETS":["VDD"], "GND_NETS":["VSS"], "SYNTH_USE_PG_PINS_DEFINES":"USE_POWER_PINS", "FP_PDN_MACRO_HOOKS":[ "dec_128 VDD VSS VDD VSS", "dec_4x32 VDD VSS VDD VSS" ] }

Reduce the die area

In your screenshot the error looks like "[ERROR GRT-0076] Net net143 is not properly covered." That sounds like maybe the ports on your macros might not be aligned to the routing grid, so it's having a hard time connecting to them. Try opening the design in the openroad gui to get a visual of that net.

Could you share your

macro.cfg

also? And are your two macros (GDS files) digital designs hardened by OpenLane?