open-source-silicon.dev

Hello all, we need to use 1.8V isolated NMOS devices. From the PDK documentation (<https://skywater-pdk.readthedocs.io/en/main/rules/device-details.html#spice-model-information>) we see that you can add deep Nwell (DNW) layer, can anyone confirm that this allows to generate such isolated 1.8V NMOS transistors?

I think you need to add LVPWELL inside of DNWELL to get isolated NMOS

<@U01EK2VDMDG> thanks for your reply
where can I find references about this? the SKY130 readthedocs page is not showing much

<@U016EM8L91B>, do you know maybe where can I find info about the LVPWELL layer?

<@U0285R77C4W> Are you talking about sky130, right? I don’t remember seeing `LVPWELL`, but I may be mistaken. The sram macros are all isolated nmos so you can check that layout.

<@U017X0NM2E7> indeed, SKY130
cool, I'll check those out :slightly_smiling_face:

<@U0285R77C4W> and <@U017X0NM2E7> I stand corrected. LVPWELL only in GF180MCU. Sky130 is diff

It’s not crystal clear from the DRM but it seems that DNWELL with nwell donut should do it.

<@U0285R77C4W> Take a look at DNwell and Nwell tables here:

<https://skywater-pdk.readthedocs.io/en/main/rules/periphery.html#dnwell|https://skywater-pdk.readthedocs.io/en/main/rules/periphery.html#dnwell>

Confirmation from foundry would be helpful about 3D crossection

<@U0285R77C4W>:  Yes, I believe that what you want is a deep nwell structure.

Yes, with nwell ring overlapping the edges of the deep nwell layer.

Sorry to exhume this thread, but are the isolated nmos devices equal in performance to their un-isolated cousins? Or do they need a different spice model?

<@U02A4K5TG5B>:  This differs from foundry to foundry.  Both Sky130 and GF180MCU use the same device model for the deep-nwell vs. nwell devices and for the p-well vs. substrate devices.  I find it hard to believe that there is no performance difference between the two, but those are the models the foundry provides.