Hello everyone. I'm trying to design a biasing circuit, a high swing MOS cascode current mirror to be precise. The schematics and result are attached here. Transistors M1-M5a have same sizings. Since Transistor M1 is biased to 1.45Vov , the width of transistor M5b is 1/5 of the width of M5a. However, the result screenshot I attached is not as expected. Some of the transistors are not conducting the correct quantity of current they are expected to conduct. The Vdsat of M1 is ridiculously high --- 8.273e+03! Also I noticed that when I make the width of M5a W/6 and the width of M5b W/5 all result are close to expected values. I tried this for other designs and it worked. But this does not follow the theory for this biasing circuit. Please help me, I need insights. I don't know why I'm observing these behaviours. Thanks in advance.

See, vt is about 0.7 V and VGS is about 2.0 V. You should bias it with a smaller current. Try 1 uA and see the results. Try also to make a DC sweep simulation at the output, instead of just using 3.3 V.

Okay I will. But this biasing circuit will be added to amplifier circuit and the maximum current in one of the major branch is 100uA and the supply voltage is 3.3V. That's why 100uA was used.

The you are going to need more transistors in parallel.

Okay. Please are you talking about the cascode stack?

Try first a basic current mirror. After that you try the high swing one.