samarth jain
08/11/2023, 9:08 AMMitch Bailey
08/11/2023, 1:52 PMcvc.oeb.report
.
If you can find that, but the messages are not clear, let me know.Marwan Abbas
08/13/2023, 7:18 AMverilog/rtl/user_defines.v
samarth jain
08/23/2023, 8:54 AMsamarth jain
08/23/2023, 8:59 AManalog_io[28:0]
but how come the user_defines have GPIO 5 TO 37 as analog?is it because gpio 5,6 are uart and how about GPIO 36,37?Kindly help to verify if my settings r ok @Marwan Abbassamarth jain
08/23/2023, 9:16 AMMitch Bailey
08/23/2023, 9:56 AMuser_project_wrapper
, analog_io[28:0]
correspond to gpio 35:7.
From caravel_user_project/verilog/rtl/user_project_wrapper.v
// Analog (direct connection to GPIO pad---use with caution)
// Note that analog I/O is not available on the 7 lowest-numbered
// GPIO pads, and so the analog_io indexing is offset from the
// GPIO indexing by 7 (also upper 2 GPIOs do not have analog_io).
inout [`MPRJ_IO_PADS-10:0] analog_io,
If you use GPIO_MODE_USER_STD_ANALOG
, set io_oeb
to low. (high is also ok since the output driver is disabled). Leaving io_oeb
open may result in an internal leak in the USER modes.
You can also choose GPIO_MODE_MGMT_STD_ANALOG
. In this case io_oeb
can be open.samarth jain
08/23/2023, 1:07 PMMitch Bailey
08/26/2023, 9:10 PMGPIO_MODE_MGMT_STD_ANALOG
and GPIO_MODE_USER_STD_ANALOG
is MGMT_ENABLE
. However as you can see from the schematic, MGMT_ENABLE
does not affect PAD_A_ESD_0_H
which is what the analog_io
connects to.
You can look at the schematics and the gpio_control_block rtl.