@Mitch Bailey I see digital io mprj_io pins are 0 to 37 index.can all these pins be used for input analog signals? These signals are 0 to 3.3V small supplies

Unfortunately, all the gpio pads for caravel can not be used for analog input. Additionally, the indices are offset from the digital i/o. From

caravel_user_project/verilog/rtl/user_project_wrapper.v

// IOs
    input  [`MPRJ_IO_PADS-1:0] io_in,
    output [`MPRJ_IO_PADS-1:0] io_out,
    output [`MPRJ_IO_PADS-1:0] io_oeb,

    // Analog (direct connection to GPIO pad---use with caution)
    // Note that analog I/O is not available on the 7 lowest-numbered
    // GPIO pads, and so the analog_io indexing is offset from the
    // GPIO indexing by 7 (also upper 2 GPIOs do not have analog_io).
    inout [`MPRJ_IO_PADS-10:0] analog_io,

So

analog_io[28:0]

are available. These go to the same gpio cells as

io_in[35:7]

Thanks also I see there r two user project templet.as my is a analog circuit,which one should I use?user project or user analog project?the user analog project does not align with this below templet given to me by efabless

Whether you use

caravel_user_project

or

caravel_user_project_analog

depends on whether you need bare pads or not.

caravel_user_project_analog

has 11 pads that have no esd or other connections, so you can use any voltage. It also has 27 normal gpio pads, 18 of which you can use as analog i/o with or without esd resistors.

caravel_user_project

has 38 gpio pads, 29 of which you can use as analog i/o with esd resistors. gpio analog signals should be between 0 and 3.3V. If you need anything outside that range, use

caravel_user_project_analog

. Also use

caravel_user_project_analog

if you need power supplies other than 0.0V, 1.8V, or 3.3V.

Hi David,Thanks for your reply.So in summary I can connect my analog inputs to chip at pins io_in[7] to io_in[35] ? I find these pins also come with something called io_out and io_en.I suppose they r same as LA in,out and en. So basically I can ignore io_out and io_en if I have only input analog signal to chip?

On a caravel frame, the

user_project_wrapper

pins

analog_io[28:0]

will connect to the corresponding gpio cells for the digital

io_out[35:7]

cells. For any cells used for analog I/O, I recommend you set the corresponding digital

io_oeb[*]

signal to high, although this might not be necessary depending on your

verilog/rtl/user_defines.v

settings. The LA in, out and en signals are completely different. They are connections to the logic analyzer in caravel’s risc-V processor.