While synthesizing caravel_user_project ,Wire user_proj_example.\wbs_dat_o is used but has no driver for example project itself

@NITHIN KRISHNAN Are you using the default

user_proj_example

? If not, you probably want to share your rtl verilog.

Yes, with the counter

From

verilog/rtl/user_proj_example.v

assign wbs_dat_o = rdata;
...
    counter #(
        .BITS(BITS)
    ) counter(
...
        .rdata(rdata),
...
    );

endmodule

module counter #(
    parameter BITS = 32
)(
...
    output [15:0] rdata,
    output [15:0] count
);
    reg ready;
    reg [15:0] count;
    reg [15:0] rdata;

    always @(posedge clk) begin
        if (reset) begin
            count <= 0;
            ready <= 0;
        end else begin
...
            if (valid && !ready) begin
...
                rdata <= count;
...
            end
        end
    end

wbs_dat_o

is assigned to

rdata

which is assigned

count

. Where do you see no driver?

In the synthesis log. make user_project_example Checking module user_proj_example... Warning: Wire user_proj_example.\wbs_dat_o [31] is used but has no driver. Warning: Wire user_proj_example.\wbs_dat_o [30] is used but has no driver. Warning: Wire user_proj_example.\wbs_dat_o [29] is used but has no driver.

gf180mcu or sky130?

sky130 commit bc4ccfec4b35d19220740f143ff1798fdfa4f0eb (HEAD -> main, tag: mpw-9a, origin/main, origin/HEAD) Author: Jeff DiCorpo <42048757+jeffdi@users.noreply.github.com> Date: Sat Mar 4 173411 2023 -0800 update tag to mpw-9a

I get the abc error, but not the other ones. Does the openlane version match?

$ cd $OPENLANE_ROOT
$ git log
commit a35b64aa200c91e9eb7dde56db787d6b4c0ea12a (grafted, HEAD, tag: 2023.02.23)

Do you use

make user_proj_example

from the

caravel_user_project

directory?

commit a35b64aa200c91e9eb7dde56db787d6b4c0ea12a (grafted, HEAD, tag: 2023.02.23) . Yes , I use

make user_proj_example

from the

caravel_user_project

directory

Ok, I see the warnings now. Looks like noise (something that can be ignored.)

Ok. Thanks David.