Hi! I would like to know the specs of the RISC-V processor in the caravel. https://caravel-mgmt-soc-litex.readthedocs.io/en/latest/#processor It's mentioned that the processor core is based on a VexRiscv minimal+debug configuration. What does that mean? Also what is the pipeline stage depth? Thanks in advance!

You can find more information about the VexRISC core here: https://github.com/enjoy-digital/litex. Otherwise, the readthedocs entry is the automatic documentation generated by LiteX when it builds the VexRISC verilog code.

Thanks @Tim Edwards Also what configuration should I provide to get the exact same VexRiscv Verilog code present on mpw-2 caravel? Like pipeline depth.. Cache size etc https://github.com/litex-hub/pythondata-cpu-vexriscv/tree/master/pythondata_cpu_vexriscv/verilog#configuration-options- Something like this. Here they gave the config for VexRiscv-Lite. Similarly what's the config for VexRiscv-minimal+debug which is present in the mpw-2 caravel?

The parameters going into the LIteX build should be found in https://github.com/efabless/caravel_mgmt_soc_litex under the

litex/

subdirectory. However, I am not familiar with the details of how the LiteX build works. (Edited: URL has underscores, not dashes)

Yes I got the above the link I sent from the link you mentioned. Also any idea of the pipeline depth present in the caravel?

Note that my original link is github, not readthedocs. Slack just auto-generated the listing for the readthedocs entry.

Yes I got that.

Just wanted to make sure. There's nothing in the configuration that modifies the pipeline depth, so it's whatever is defined by default for the LiteX VexRISC, but I don't know what that is without researching it.

Okay. I get it. From the link, it seems that they fixed pipeline depth as five and added configurations to it. Since the area occupied by VexRiscv in the caravel is very small, I was confused that it might have a lesser pipeline depth.

I have pointed out multiple times in the past that the VexRISC is a poor choice for the Caravel SoC due to the limited space. It's not the pipeline depth that is the problem; it is the instruction cache. Due to the limited area available for memory, the instruction cache is very small, and the pipeline is poorly utilized. Extremely poorly utilized. The effective processing rate of the VexRISC on Caravel is about 10x slower than the original PicoRV32 implementation. The VexRISC architecture was not designed for tiny embedded systems with low memory overhead.

Hmm makes sense. Thanks a lot for your help!