Could someone point me to detailed documentation o...
# caravel
m
Could someone point me to detailed documentation on the logic analyzer? Aside from the wrapper verilog and a couple notes online I can't find anything after a lot of hunting. Certainly there's some specific documentation on the interface description for this and the wishbone bus?
m
I'm afraid there isn't much. Here's the machine generated register defs for the litex management core: https://caravel-mgmt-soc-litex.readthedocs.io/en/latest/#logic-analyzer
m
Thanks! I found a picture in one of their old youtube videos that gives some explanation in case anyone else is looking:
Untitled.png