Hi I'm using standard cells for frequency divider (8:1) using DFF. However, 8kHz input is given and it stick to 2kHz not getting down to 1kHz even if number of FF is increased. What could be the reason? I'm I missing something? Attached ngspice window showing measurements in time. Like for VA, period is 0.125mSec. Vb is 0.25mSec. Vc is 0.5mSec and same for Vd, Ve. Which expected like Vd at 1mSec. And going down further with number of FF

5us rise and fall time for the clock is too much use 1ns rise/fall time and reduce tran step size. This might not solve the issue, but who knows...

Thanks for giving hint. actually i have to play with timing & step size as if i take step size low as 1nSec and for 1kHz freq to observe tran period has to be high and spice take very very long time like more than 40min to get result. but i do get the concept. 👍

can you plot Va Vb Vc Vd and Ve ?

1. just use higher frequency 2. You sure, you are not having hold time violations?

The divider works, but the first stage driven by

clk

does not, since the rise and fall time of the clock is far too big. Using 5ns rise / fall time makes the circuit work.

Thank you everyone! However I solved it on last day. And so marked this as ✅ . And Stefan you are great help!

As a side note: always reset flip flops with a reset pulse so you start from a known condition.