Hi, i'm trying to make frequency divider (8:1) circuit using standard cell using SKY130, xschem, ngspice. But upon simulation its doesn't work as expected. also, reset doesn't affects whether it's getting tied to logic 1 i.e. 1.8v or logic 0 i.e. gnd. can someone help me...

There is no power supply.

And what could be the power pins? Bdw just now I tried putting a voltage source of 1.8V and used labpin with name VDD. Still no change.

looking at dfrbp_1.sym I see that there are four extra pins declared: VGND VNB VPB VPWR

Thank you @Jecel Assumpção Jr. I'm using stdcells first time. And wasn't aware of subscircuit pins for the DFF.

Looking at the spice definition for the flipflop in sky130A/libs.ref/sky130_fd_sc_hd/spice/sky130_fd_sc_hd.spice I see that the VNB pin is connected to all the nfet transistors and VPB to all the pfet ones. These are the "bulk" pins and should be 1.8V for VPB and 0V for VNB

I put it like this and now this error appears as, doAnalyses: too many iterations without convergence Error: no such vector vin But it was working/ simulating error without any error and now I just added a voltage supply VPWR -- 1.8V -- VGND.

both vpwr and vpb are close to 0. You should check your generated netlist to see if things are connected as you think they should be

Until now I am depend on xschem features of generating netlist automatically. However looking at netlist I don't think anything is wrong. But still, am I missing something? Same spice error as no such vector and doAnalyses: too many iterations Note I changed vin name to clk and redrawn the schematic and then checked the netlist.

VPB and VNB are still not connected to anything

Also, try .tran 1n 2u uic Flip flops have unknown states during initialization. That is why you should start your simulation with a reset pulse. Otherwise, you should set the initial conditions.

Thank you so much @Jecel Assumpção Jr and @Luis Henrique Rodovalho. I'll try it again after dinner. Have a nice time!

Just to be clear standard cells have power and body connections set by attributes. Select a standard cell , press 'q' to edit its attributes and you see the implicit power connections. Avoiding physical pins on standard cell symbols makes the design more clean, you don't have to wire power nets or labels everywhere and usually all standard cells in a given domain have all identical power/body connections.

thanks a lot @Stefan Schippers for clearing me about standard cells, as i wasn't aware of it. I made the changes. However, the output (Va) is not as expected. and how it can go cross the zero line. weird response. am i doing anything wrong?

I think you must tie VSS to the 0 node... Add this:

vvss vss 0 0

or equivalently:

vvss vss gnd 0