I am trying to add a constraint on the generated clock using "create_generated_clock" but the problem is when I add the option of "get_ports " the tool fails to read the hierarchy name so is there any one here that can help me or tried before to do this on yosys tool

for better understanding share the log and command you tried

I tried to define the generated clock as in -line 4- inside the base.sdc file but this the error that was generated after synthesizing

There are too many things need to be fixed. Better raise github issue here https://github.com/The-OpenROAD-Project/OpenLane/issues with required

src

and

config.json

to check the same. From your design, which is your clock port?

This the top system

which version of OpenLane you're using?

Version 0.9

its very old. follow this step and install from here for latest OpenLane https://github.com/The-OpenROAD-Project/OpenLane#installation-the-short-version

I installed it from this link but it seems there was a misunderstanding from as the package required was 0.9 but i don't if this refers to openlane version or not