So I've seen Yosys "kGE" (kilo gate equivalent) listed for area on a few projects. How does this compare to the gate count in the OpenLane Skywater 130nm std-cell gate count?

When i install ngspice and try to execute the command ../configure --with-x --with-readline=yes I am getting an error "configure: error: Couldn't find GNU readline headers. " Can anyone help me how to fix this, I did try to install "sudo apt-get install lib32readline8 lib32readline-dev sudo apt-get install libxaw7-dev "and still unable to resolve the error And when I give $MAKE command it isn't able to execute even though the file contains make file Git repo link that i cloned: git clone git://git.code.sf.net/p/ngspice/ngspice Website link that i referred : https://ngspice.sourceforge.io/gitaccess.html (The Pre master command also hadn't executed)

Hello, I encountered an LVS error. It seems the error is related to mismatched pin names of MOSFETs. Done anyone know how to solve it?

This is regarding pin_order.cfg file for user_proj_example. I got the following error with my example project. _*Valid directives are #N, #E, #S, or #W. Append R for reversing the default order. Use #BUS_SORT to group 'bus bits' by index. Please make sure you have set a valid side first before listing pins*_ child process exited abnormally Is there a document where I can refer to know more about the #N/E/S/W/R and $BUS_SORT. How to write pin_order.cfg file? wb_.* etc. mean what?

Hello, I'm starting to use magic for layout and I was wondering it is better to instantiate each sky130 device separately or just import the devices straight from the spice netlist. I ask because when I import from the spice netlist, the devices are automatically generated with a guard ring, and I don't really know if the guard rings are needed all the time for all the devices. Thank you.

I'm trying to generate SDF to use in simulation but am having problems. In the Parallax SDF documentation, write_sdf has several options : write_sdf [-corner corner_name] [-divider /|.] [-include_typ] [-digits digits] [-gzip] [-no_timestamp] [-no_version] filename The command for write_sdf is or_sta.tcl in which is called by routing.tcl in OpenLane scripts; however, when I try and add the option, '-include_typ', the command fails. I want to include the typical value in the SDF file so that Icarus Verilog sdf_annotate command will work properly.

@User I am trying Synopsys tools for an open-source FPGA IP generation based on the skywater PDK. Currently, I am blocked by the technology file. If you can share your experience, it will help a lot. Thanks!

Hello all, Hope everyone here is well I have a basic doubt from xschem can anyone suggest me that how can I give the sine input voltage source in xschem circuit ?

hi, now I'm getting this error in my project in open lane "[ERROR]: There are hold violations in the design at the typical corner", this error point me to a file with the timings. What I need to change to fix the hold violation error?, increment target density, bigger chip, etc ..

Is OpenRoad and QFlow are different?