So I've seen Yosys "kGE" (kilo gate equivalent) listed for area on a few projects. How does this c...
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So I've seen Yosys "kGE" (kilo gate equivalent) listed for area on a few projects. How does this compare to the gate count in the OpenLane Skywater 130nm std-cell gate count?
OK a little more digging looks like is an "area estimate" that would include memories and hard IP cells converted to a 2-input NAND gate equivalent for area purposes. Still curious how kGE compares to Skywater 130nm std-cell gate count.
I guess my question boils down to does anyone have a quick ratio for Skywater 130nm gate count to kGE? OR... is there a way to get Yosys to output the kGE within the OpenLane flow?
a
i dont think this metric is any useful. Just use the yosys output netlist area. Since one gate of sky130 ratio to kge will be significantly different between RTLs
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I understand using the target RTL and target std-lib gives the actual area. And you're right a conversion ratio would be a very rough estimate. The reason I'm asking for for the sake of estimation when reviewing an IP or reading published papers. Is there a switch in OpenLane that triggers yosys to output kGE results alongside the skywater 130nm results?
a
one nand gates is one "gate element" you can use nand2 gates area to calculate the kGE to area ratio
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