Does anyone know a good GUI for visualizing

ngspice

simulation results ? The built in one is ... not great.

How is the local interconnect different from a metal layer ?

I get the following error during synthesis

ABC: Error: The network is combinational.

. Any idea how to get around it? or what might be causing it? Thanks for the help!

Hi everyone, I have successfully synthesized my design using Yosys and the sky130_fd_sc_hd process. Now, I'm looking to perform gate-level simulation on the synthesized design using Verilator. However, most of the examples for gate-level simulation use Icarus Verilog (iverilog) as the simulator. I'm wondering if anyone has experience with gate-level simulation using Verilator. Could someone please provide guidance or share their experience? Thank you.

How to rectify ' volare: command not found'?

Is there a way to specify multiple clocks with their own max frequencies in openlane? So it would generate 2 clock trees and be able to do sta on both clock domains?

Hi, I'm new around here. I started using iic-osic-tools and I'm in doubt on how to configure OpenLane, could someone help me?

Hello, for some reason I am getting a DRC error with Caravel when trying to do a tape out on efabless. Can somebody help? This is the error: STDERR: [ WARN ] Poly Density Check Result: 'caravel_24114807.oas' has 1132 DRC violations.

Has anyone used the XSPICE extension of NGSPICE? If so, how would you rate your experience with XSPICE?

Hi all, I am trying to design a circuit using transistor models "g5v0d10v5". The circuit has a supply voltage of 5V. I am trying to run monte carlo simulation to see different the affect of process variation in the design. The MC simulation is not running. When I use 1.8V transistors, the monte carlo simulation is running. Can anyone please help me with the issue? Please see the attached image of the setup.