Hello all, I'm a beginner in using XSchem and NGspice and I was facing some troubles in simulating my first circuit which is a track and hold circuit. After I create the netlist successfully and try to simulate it I get a whole bunch of errors that I don't know the reasons behind them. I'll attach the circuit, the script for the clock voltage source, the ngspice commands and the errors window. If anyone can help me, I'll be very thankful.

How to rectify ' volare: command not found'?

Hi everyone! Where can I see a more detailed error log for Yosys? For the function Checker.YosysSynthChecks. I got an error during hardening, where it says " ERROR 221 Yosys check errors found." Checked the yosys-synthesis.log, I have found one error which said ABC: Error: The network is combinational. Wonder if it's the "221 Yosys check errors found." Yosys was refering to. Is there anyway to solve the ABC error?

This is regarding pin_order.cfg file for user_proj_example. I got the following error with my example project. _*Valid directives are #N, #E, #S, or #W. Append R for reversing the default order. Use #BUS_SORT to group 'bus bits' by index. Please make sure you have set a valid side first before listing pins*_ child process exited abnormally Is there a document where I can refer to know more about the #N/E/S/W/R and $BUS_SORT. How to write pin_order.cfg file? wb_.* etc. mean what?

Hi all, I am trying to design a circuit using transistor models "g5v0d10v5". The circuit has a supply voltage of 5V. I am trying to run monte carlo simulation to see different the affect of process variation in the design. The MC simulation is not running. When I use 1.8V transistors, the monte carlo simulation is running. Can anyone please help me with the issue? Please see the attached image of the setup.

Is OpenRoad and QFlow are different?

@Tim Edwards Is there a way to do a gate level sim with sky130 in Icarus with sdf annotation? It looks like the stdcells verilog I have is not annotated with timing information, so I see this error: “Omitting $sdf_annotate() since specify blocks are being omitted”. Is there another verilog file available with the specify blocks? Thanks!

I have spent a few hours over the weekend really trying to design with the BJT/HBT models. But I am having little luck. The noise figure simulations seem to be fixed once non-ideal components are used. but I am still worried that it is a bad extrapolation that is causing the weird behavior. Once I realized the NF is believable (at least) I started designing matching circuits. At 60 GHz this needs to be distributed components. But I cannot seem to make the models work in ng-spice with S-parameter touchstone files. So, I would simulate using open EM, and generate a s2p file. But then the s-parameter sim in ng spice just bombs out on me. Has anyone designed with SnP files so far? Any advice? 🙂

Hi All, I am trying to design an ESD protection circuit since I am planning to use 11 analog pins in caravan wrapper which has no ESD protection. I tried simulating the available diode model diode_pw2nd_05v5 using the combined models. I changed the device name from D to XD. After simulation, I am getting a forward voltage of around

1.78V

required to turn on the diode (image is attached). Is that result correct or am I doing something wrong? Moreover, I can not find any ESD specific devices other than some nfet and there as well I can not find any difference in layout. Can anyone please help with what devices to use and how to simulate it properly. I also tried simulating

test_esd

circuit provide by @Stephen Schippers. I simulation is not running properly. Can anyone please help me with the issue?

I have a black boxed inverter macro that has vdd and gnd as power pins.I connected these pins with vdda1 and vssa1 as I am using 2 analog pins as input and output.Then I got an error at step 40 of hardening user_pro_example that no pins are marked as POWER or ground in LEF.Then I added in the LEF file "USE POWER ;"and "USE GROUND :"and got rid of the error.Now it is failing LVS at step 42.In layout I have vdd and gnd pins, but not explicitly defined as power pins.I have attached the snapshot of LEF and verilog file.Please help me to fix the error.