Is there a way to specify multiple clocks with their own max frequencies in openlane? So it would generate 2 clock trees and be able to do sta on both clock domains?

Hello, I'm trying to run LVS directly in Klayout, however, I haven't been able to do it. It always shows the error in the image. It says I haven't set the schematic, however, I haven't found where to set the schematic netlist.

Hi, I'm new around here. I started using iic-osic-tools and I'm in doubt on how to configure OpenLane, could someone help me?

In a 3-well process (nwell, pwell, deep nwell) there are 5 types of diodes. pdiff - nwell, pwell - ndiff, psub - nwell, pwell - deep nwell, psub - deep nwell (if psub is not virtually split, psub - nwell and psub - deep nwell are electrically equivalent). From what I can see, the magic extraction rules only handle pdiff - nwell and pwell - ndiff. @User Is this correct?

Hi, I am new to efabless tape out process and the use of open source tools. I have designed a two stage opamp to understand the design and tape out process for analog circuits. While running precheck locally, the GPIO-Defines check is failing. I have edited the user_defines.v file as suggested but the error is still present. Please see the attached user_define.v file and precheck log. Moreover, the precheck is not running LVS. The caravel was initially installed for digital designs (MPW8) with user_project_wrapper but I cloned an user_analog_project_wrapper and followed the steps with the old CARAVEL_ROOT path. Is that creating the issue? Please help me with the issue.

Hi everyone, I am working on the layout with sky130 pdk, and I want the allowed current density for each metal line interconnect for my design. I tried searching the documentation but couldn't get any information on this. Can anyone help me with this information, or how I can calculate it theoretically? @Stefan Schippers @mehdi

Hi all, I am trying to design a circuit using transistor models "g5v0d10v5". The circuit has a supply voltage of 5V. I am trying to run monte carlo simulation to see different the affect of process variation in the design. The MC simulation is not running. When I use 1.8V transistors, the monte carlo simulation is running. Can anyone please help me with the issue? Please see the attached image of the setup.

@User I am trying Synopsys tools for an open-source FPGA IP generation based on the skywater PDK. Currently, I am blocked by the technology file. If you can share your experience, it will help a lot. Thanks!

I'm trying to generate SDF to use in simulation but am having problems. In the Parallax SDF documentation, write_sdf has several options : write_sdf [-corner corner_name] [-divider /|.] [-include_typ] [-digits digits] [-gzip] [-no_timestamp] [-no_version] filename The command for write_sdf is or_sta.tcl in which is called by routing.tcl in OpenLane scripts; however, when I try and add the option, '-include_typ', the command fails. I want to include the typical value in the SDF file so that Icarus Verilog sdf_annotate command will work properly.

I'm trying to learn how to work with OpenLane and I'm trying to run this example on OpenLane, but I have several issues: I made these changes in the config.tcl: set ::env(PL_TARGET_DENSITY) "0.7" set ::env(FP_CORE_UTIL) "70" set ::env(PL_RANDOM_GLB_PLACEMENT) "1" set ::env(PL_RANDOM_INITIAL_PLACEMENT) "1" But I received this error: [ERROR PDN-0108] Spacing (1.1200 um) specified for layer met5 is less than minimum spacing (1.6000 um). Error: pdn_cfg.tcl, 129 PDN-0108 How can I fix it?