help me resolve this

Hi all. I wanted to ask that is there a way in openlane to add a vcd file of design to estimate power. Thanks

Hi I’m getting this error in the openlane flow (user_porject_wrapper)

[STEP 14]
[INFO]: Writing Verilog...
[STEP 15]
[INFO]: Running Detailed Routing...
[ERROR]: during executing openroad script /openlane/scripts/openroad/droute.tcl
[ERROR]: Exit code: 1
[ERROR]: full log: ../home/mxmont/Documents/Universidad/IC-UBB/MixPix/CARAVEL_WRAPPER/MixPix/openlane/user_project_wrapper/runs/22_11_06_12_15/logs/routing/15-detailed.log
[ERROR]: Last 10 lines:
Units:                1000
Number of layers:     13
Number of macros:     443
Number of vias:       25
Number of viarulegen: 25

[INFO DRT-0150] Reading design.
[ERROR DRT-0305] Net zero_ of signal type GROUND is not routable by TritonRoute. Move to special nets.
Error: droute.tcl, 46 DRT-0305
child process exited abnormally

I check different slack channels, and I found this: https://open-source-silicon.slack.com/archives/C016H8WJMBR/p1659754025686099 proposed WA: https://open-source-silicon.slack.com/archives/C016H8WJMBR/p1662445019683969?thread_ts=1659754025.686099&cid=C016H8WJMBR I do make openlane to udapdate dependencies/openlane_src, rerun the flow and the problem still appears looks like a past bug; the WA mentioned in the thread solved the routing problem, but at the end of the flow there are LVS errors related to the fix. Is someone else having this problem with Caravel flow? The repo of the project is updated with the last changes here: https://github.com/HALxmont/MixPix

@User the nvt suffix indicates a negative native threshold, so the 03v3_nvt is a (slightly) depletion nmos. If you sweep the vgs from -1V you see the transistor turn on.

@User search for a file named (for pfet_1v8)

sky130_fd_pr__pfet_01v8.bins.csv

, (path is:

.../sky130_fd_pr/latest/cells/pfet_01v8/sky130_fd_pr__pfet_01v8.bins.csv

) you can get it here on github. This can be opened with a text editor (or for better formatting) with a spreadsheet, it lists all the W/L bin ranges. Similar filenames for other transistor types.

Released xschem 3.4.6

Hello everyone, I recently hardened several macros in my design, allowing up to metal layer 5 (met5) for routing and using vertical met4 stripes for the power connection. Afterward, I integrated these macros into a top module and added a power ring using met4 and met5 layers. This top module was then integrated into the

user_project_wrapper

. I'm wondering if this approach might present any issues because I am using a ring with met5 and mt4 in my topmodule. Specifically, I encountered a situation where I had to set

"RUN_IRDROP_REPORT": false

to avoid the following warning when integrating my top module in the user_project_wrapper: >

[WARNING PSM-0038] Unconnected PDN node on net vccd1 at location (1426.418um, 1542.240um).

Upon reviewing the design, I noticed that vias have been added to establish the necessary connections. Does anyone have insights or suggestions on addressing this approach is ok?

Hello, This is related to the IP hardening process. From the tutorials on efabless.com, I understand that IP hardening is 2-step process (1: Harden your design, 2: Instantiate the netlist within user_project_wrapper and then harden the complete wrapper). Can we simply instantiate our custom RTL in user_project_wrapper and harden only once?

Is there a way in xschem to mark some components as bypassed or non existent for LVS ? Like I'd like to include some caps that are only simulating the parasitics during sim but shouldn't be on the LVS netlist. Or including

ampmeter

that also abviously be replaced by short during LVS.

Anybody happen to have a white noise generator that I could blindly use? I need one. My impression is that it won't simulate properly with ngspice so you have to use Actual Understanding to make it (which I lack).Been banging my head all day trying to make one myself.