@Tim Edwards @Tim 'mithro' Ansell @mkk Any idea about the availability date of the SKY90 open-source PDK?

Hi everyone, I've just installed OpenLane, generated the test

spm

project with

$ make test

, and I'm now staring at the

spm.gds

file through the latest build of KLayout. However, one thing that is confusing is the layer naming (see attached screenshot) - I've told KLayout where to find the

Sky130A.lyp

file, but I'm still getting stuff on layers with no real name - could anyone suggest what's the meaning of these layers?

most are using xschem but I've had a little luck using qucs-s (the qucs gui with spice backend)

Hi there! I would appreciate some help with this. I have successfully run OpenLane flow with a simple counter design, with sky130 PDK. The flow has generated 74 steps from RTL to fully-verified GDSII. Now I want to check interactively the timing of specific paths through OpenRoad GUI. For that purpose I open the final ODB file under “final/odb” folder. When I open the “Timing Report” window and click on “Update”, I get the following warning in the terminal: “[WARNING GUI-0077] Timing data is not stored in … runs/RUN_2024-12-14_19-10-27/final/odb/counter.odb and must be loaded separately, if needed.“. OK, then I run from TCL console the following: “read_spef … /runs/RUN_2024-12-14_19-10-27/final/spef/max/counter.max.spef”. Then I “Update” again under “Timing Report” but do not get any information in the Setup/Hold tabs. What are the next steps to check timing paths interactively? What are the recommended “Settings”? I would like to see what is shown by @Matt Liberty in the following video (from 5:13):

Hello everyone, I'm trying to perform an ASIC flow with Openlane and encountering some issues that I need help with. First, let me explain the error I'm getting. The error message is [ERROR GRT-0119] Routing congestion too high. Check the congestion heatmap in the GUI and load. Initially, I thought the cause might be FP_CORE_UTIL, so I changed this value to 30, but I still encountered the same error. When I looked into the Slack channel, I understood that I need to use FP_PDN_MACRO_HOOKS, but I couldn't grasp its correct usage even after reviewing the Openlane documentation. Could someone tell me how to do this? Apart from this, I haven't added the Base_sdc_file command and file to the chip flow. What impact does this have on the flow, and is it necessary to add it? Finally, I want to add a Pin_order.cfg file. How can I do this? I appreciate your assistance! There are lots of module on my code.

Hello everyone, I am currently going through various resources on SRAM design focusing on memory clock signal generation. I have found that most of the existing designs use external clock signal, and some designs use that external clock as a reference for internal clock generation. Most of the cases this external clk comes from the CPU. In our previous SRAM design, we have used external CLK from CPU, that means, we didn't need to work on CLK circuitry. Now, we want to design an on-memory CLK for the 32*1024 SRAM with the peripherals. Now, I wanted to seek your guidance on the necessity and feasibility of generating the clock signal entirely within the SRAM cell itself. Specifically, is it essential to find a method for internal clock generation within the SRAM? Or I also should follow the conventional approach to design internal clock generation circuit which will be engaged to generate clk for the memory but based on the external reference clk signal? Or Self-Timed (Asynchronous SRAM) approach should be followed? I would greatly appreciate your insights on this matter. Thank you so much in advance.

Hi All, I have one question regarding MIM caps in sky 130 pdk. I do not see any antenna rules in DRC for

mim caps

. However, the lower metal layer of mim cap is already connected to upper layer using via in parametric cell. Is that enough to not have any antenna violation or should I consider something else as well in my design? Please tell me if anyone knows any other design rule I should follow while using mim caps.

Hi everyone, has anyone successfully used the second clock in Caravel (user_clock2) , alongside the 'main' wishbone clock (clk)? Does it function the same?

hi everyone. Suppose I instantiate a MOS in Xschem and tell it to be

W=10

and

nf=2

. When I open up an empty

.mag

file in Magic and do

Import SPICE

, I get a MOS with truly 2 fingers, each 5 width, so that's great. However, the diffusion contacts are overlapped... That, itself, wouldn't be a problem - if I Magic was able to extract the middle node as source. What Magic does at extraction is: • it calls the left diffusion of the left finger a source, and its right diffusion a drain. • it calls the left diffusion of the right finger a source, and its right diffusion a drain. That, further, means that these two fingers are actually connected in series... and I don't want that. Can I perform

Import SPICE

in a way that MOS devices with multiple fingers are generated without diffusion contacts overlapping? Or, even better, can I get them with diffusion contacts overlapping, but in such a way that diffusions are treated as:

D (finger1) S (finger2) D

so that both left and right finger get source contact in the middle?

Hi, I have an issue regarding setting constraints with hierarchical paths. I believe the issue is caused by Yosys flattening the netlist and not regenerating the SDC constraints with the updated paths. This is then causing the constraints to not be recognized as many of the signals were renamed and the hierarchy was lost. Not flattening the netlist doesn't fix the issue either. By default Yosys doesn't seem to have the feature to rewrite sdc constraints, I've tried using the following plugin: sdc-plugin for Yosys, which adds support for read_sdc and write_sdc, but the generated SDC constraints are also based on the pre-synthesis RTL (not compatible with the post synthesis netlist). This is causing issues in the flow since STA is not able to recognize the timing constraints. Adjusting the constraints manually to match the post-synthesis netlist seems to work, however, the netlist is quite large and there are many SDC constraints so that is not really feasible for my project. Is there a solution to this other than adjusting the SDC constraints according to the post synthesis netlist?