@Amro Tork @Krzysztof Herman I have a question on how to properly setup the IHP PDK for KLayout. In some situations (like on our IIC-OSIC-TOOLS image) the PDK sits in a read-only location, and even the user home directory is read-only. How should one setup KLayout and environment variables properly for this to work? E.g. accessing the right

.lyt

and

.lyp

files, and especially properly finding all the Python stuff? I am not sure that the current setup (if I look into the

.lyt

for example) supports such a usage model. Here is a GH issue to track the discussion: https://github.com/IHP-GmbH/IHP-Open-PDK/issues/87

#magic anyone have experience with antenna checks in Magic? If so, do you see a challenge running the antenna checks on a flat design? Background: I have a SAR, and when I run antenna checks on a hierarchical design I get a bunch of antenna check errors (some obviously wrong). When I run flat, however, all antenna errors disappear. Now, am I fooling myself in trusting the lack of antenna errors on my flat design 🙂

Couple of questions about simulating the netlist I get from parasitic extraction. I checked this recent video:

Dose 'klayout' widely used for editing layouts in this open-source field? I developed scripts to connect laygo2 and magic for design automation(Example). If the klayout is also commonly used, I could make similar scripts for klayout.

I have a question about generating the power grid through openlane. I have to bring in analog blackboxes that use mimcaps through m3-m5 so I can't have the PDN grid cover the entire chip. I tried metal obstructions but since the PDN gets generated first, I am trying to keep the grid out of the analog area with halos:

set ::env(FP_PDN_HORIZONTAL_HALO) 420

set ::env(FP_PDN_VERTICAL_HALO) 420

But I am not quite sure how this works...the horizontal power straps persist. Is there to disable both horizontal and vertical stripes in the halo area?

i build

skywater-pdk

from HEAD by following the instructions. i have

magic

v 8.3.305 installed. i then try to install

open_pdks

by pointing to this and i get the error:

Error:  Magic version 8.3.306 is required by this techfile, but this version of magic is 8.3.305.

but i can't install magic 8.3.306 because I get this linker error on compile (and I don't get it with 8.3.305):

/usr/bin/ld: /usr/lib/gcc/x86_64-linux-gnu/10/../../../x86_64-linux-gnu/Scrt1.o: in function `_start':
(.text+0x20): undefined reference to `main'

how do i install the pdk now?

OpenLane install is failing on M1 MacBook (BTW, I am working in Parallels with ARM64, so I guess this same error would be there for any ARM64-based machine). When I do

make openlane

the following error shows up:

Step 1/25 : FROM openlane-run-base
pull access denied for openlane-run-base, repository does not exist or may require 'docker login': denied: requested access to the resource is denied

If I try to do

make pull-openlane

it fetches the prebuilt docker image, but fails later during

make pdk

with:

[ -d /home/parallels/OpenLane/pdks/sky130A ] && rm -rf /home/parallels/OpenLane/pdks/sky130A || true
docker run --rm -v /home/parallels/OpenLane:/openlane -v /home/parallels/OpenLane/designs:/openlane/install -v /home/parallels/OpenLane/pdks:/home/parallels/OpenLane/pdks -e PDK_ROOT=/home/parallels/OpenLane/pdks -e STD_CELL_LIBRARY=sky130_fd_sc_hd --user 1000:1000 -e DISPLAY=:0 -v /tmp/.X11-unix:/tmp/.X11-unix -v /home/parallels/.Xauthority:/.Xauthority --network host efabless/openlane:0d8d4c187cb6d0af7b221b364caa2908d8cc9843 sh -c "\
	cd /home/parallels/OpenLane/pdks/open_pdks && \
	./configure --enable-sky130-pdk=/home/parallels/OpenLane/pdks/skywater-pdk/libraries ""\
"
WARNING: The requested image's platform (linux/amd64) does not match the detected host platform (linux/arm64/v8) and no specific platform was requested
standard_init_linux.go:228: exec user process caused: exec format error
make: *** [dependencies/pdk.mk:72: build-pdk] Error 1

Hi All, I’m trying to

make user_project_wrapper

and be stuck at or_pdn step. It just hang the flow then crashed (after 8 hrs?). This issue was reported before and @User suggested to make the macro smaller to get over, but our design cannot be shrunk. Does anyone encounter this issue and/or have an idea how to fix it? Thanks

Placing the following macros:
{'inst_eFPGA_top': ['40000', '40000', 'R0']}
Design name: user_project_wrapper
Placing inst_eFPGA_top
Successfully placed 1 instances
[INFO]: Changing layout from /project/openlane/user_project_wrapper/runs/user_project_wrapper/tmp/floorplan/5-ioPlacer.def to /project/openlane/user_project_wrapper/runs/user_project_wrapper/tmp/floorplan/5-ioPlacer.macro_placement.def
[WARNING]: Skipping Tap/Decap Insertion.
[INFO]: Power planning the following nets
[INFO]: Power: vccd1 vccd2 vdda1 vdda2
[INFO]: Ground: vssd1 vssd2 vssa1 vssa2
[INFO]: Generating PDN...
[INFO]: current step index: 7
[INFO]: current step index: 8
OpenROAD GITDIR-NOTFOUND 
This program is licensed under the BSD-3 license. See the LICENSE file for details.
Components of this program may be licensed under more restrictive licenses which must be honored.
[INFO ODB-0222] Reading LEF file: /project/openlane/user_project_wrapper/runs/user_project_wrapper/tmp/merged_unpadded.lef
[WARNING ODB-0220] WARNING (LEFPARS-2036): SOURCE statement is obsolete in version 5.6 and later.
The LEF parser will ignore this statement.
To avoid this warning in the future, remove this statement from the LEF file with version 5.6 or later. See file /project/openlane/user_project_wrapper/runs/user_project_wrapper/tmp/merged_unpadded.lef at line 973.

[INFO ODB-0223]     Created 13 technology layers
[INFO ODB-0224]     Created 25 technology vias
[INFO ODB-0225]     Created 442 library cells
[INFO ODB-0226] Finished LEF file:  /project/openlane/user_project_wrapper/runs/user_project_wrapper/tmp/merged_unpadded.lef
[INFO ODB-0127] Reading DEF file: /project/openlane/user_project_wrapper/runs/user_project_wrapper/tmp/floorplan/5-ioPlacer.macro_placement.def
[INFO ODB-0128] Design: user_project_wrapper
[INFO ODB-0130]     Created 637 pins.
[INFO ODB-0131]     Created 1 components and 224 component-terminals.
[INFO ODB-0133]     Created 652 nets and 222 connections.
[INFO ODB-0134] Finished DEF file: /project/openlane/user_project_wrapper/runs/user_project_wrapper/tmp/floorplan/5-ioPlacer.macro_placement.def
[INFO PDN-0016] Power Delivery Network Generator: Generating PDN
  config: /openlane/scripts/openroad/or_pdn_cfg.tcl
[INFO PDN-0008] Design name is user_project_wrapper.
[INFO PDN-0009] Reading technology data.
[INFO PDN-0011] ****** INFO ******
Type: stdcell, stdcell_grid
    Core Rings
      Layer: met4  -  width: 3.100  spacing: 1.700  core_offset: 14.000 
      Layer: met5  -  width: 3.100  spacing: 1.700  core_offset: 14.000 
    Straps
      Layer: met4  -  width: 3.100  pitch: 180.000  offset: 5.000 
      Layer: met5  -  width: 3.100  pitch: 180.000  offset: 5.000 
    Connect: {met4 met5}
Type: macro, CORE_macro_grid_1
    Macro orientation: R0 R180 MX MY R90 R270 MXR90 MYR90
    Straps
    Connect: {met4_PIN_ver met5}
[INFO PDN-0012] **** END INFO ****
[INFO PDN-0013] Inserting stdcell grid - stdcell_grid.
[INFO PDN-0010] Inserting macro grid for 1 macros.
[INFO PDN-0034]   - grid CORE_macro_grid_1 for instance inst_eFPGA_top
...
[WARNING PSM-0030] VSRC location at (2245.520um, 3230.880um) and size 10.000um, is not located on a power stripe. Moving to closest stripe at (2246.400um, 3255.880um).
[INFO PSM-0031] Number of PDN nodes on net vccd1 = 12067.
[WARNING PSM-0032] Node at (2883600, 3509465) and layer 5 moved from (2872540, 3435880).
...
[WARNING PSM-0032] Node at (189000, 10265) and layer 5 moved from (203450, 1275880).
[WARNING PSM-0032] message limit reached, this message will no longer print
[INFO PSM-0064] Number of voltage sources = 88.

I'm trying to simulate an extracted spice netlist of about 50 cells. I'm trying for 5 clock cycles over 20ns. It's taking forever! Are there any techniques to speed up spice simulation of larger designs?

Hi everyone, I'm currently working with OpenLane for synthesizing my FFT design, and I’m encountering an issue where some memories seem to be replaced by registers during the synthesis process, but I'm unsure if any modules are being blackboxed. Here’s a summary of the situation: • I’ve successfully synthesis my rtl code in yosys. • There are warnings in the Yosys log about certain memories (

\result_i_ns

,

\result_r_ns

,

\result_i

,

\result_r

) being replaced by registers. • When running the

blackbox

command, no specific blackboxed modules are reported. Any advice or pointers on how to handle this situation would be greatly appreciated! Thanks in advance! 🙏