Hi everyone, I have a question. I am trying to synthesize my mMIPS processor usuing asap7 technology. But I am getting this error continuously. I guess it is because it is not able to find eqy. But I checked the path for eqy and added it to the bashrc file. Even after that I am getting the same error. And when I try to synthesize some example core already given in openroad, then it gets stuck at the end with the error that "unable to repair all setup violations" and "couldn't find eqy, no such file or directory" . One of the solutions I found was to download eqy and yosys again using "oss-cad-suite build" from : https://github.com/YosysHQ/oss-cad-suite-build/releases and re installing openroad using "pre-built binary installer" from : https://github.com/Precision-Innovations/OpenROAD/releases. But the thing is i am at a critical stage of my project and re installing everything could be risky. That's why I wanted to ask is there another solution to this? If someone could advice, that would be really great. Thanks

Can anyone tell me why my klayout is not opening in default mode, also I want to load it with sky130pdk how can I do it ?, when I was trying to add sky130 layer porperties it is showing the following error how to resolve it ?

Hello, I use a custom PDK over OpenROAD. On the Yosys side, it replaces all the cells with those defined in the Liberty file. Although

LOGIC0

and

LOGIC1

are defined in the Liberty file, the don't_use variable is true for both of them, so Yosys doesn't utilize them. However,

LOGIC0

appears as one of the cells in the final GDS file generated by OpenROAD. How can I prevent OpenROAD from using

LOGIC

cells and force it to use the cells synthesized by Yosys?

Hi to all. What is a guard-ring? How can I tell if my (quite complex) circuit needs them? I'm using a non-standard CMOS design, although I do use discrete voltage levels.

@Stefan Schippers: Is is possible that when a schematic file is read in xschem, that the intepretation of "cwd" can be relocated to the location of the schematic being read? This would make projects using xschem schematics more portable. The problem is that I am trying to use entire projects as dependencies of other projects; I have, for example, a project called

sky130_ef_ip__analog_switches

which is a library of analog switches. It is all self-contained, so it has an "xschem" directory, and all the schematics in that directory include components from the same directory. If I want to use those switches in another project, then I create a directory called "dependencies" in that project, and under "dependencies" I clone the

sky130_ef_ip__analog_switches

repository. Then I can include a switch symbol by navigating to the repository and choosing a switch symbol. However, that symbol is linked to a schematic, and that schematic may refer to other symbols in the same directory. If so, then xschem cannot find those symbols. But it can find the schematic linked to the symbol, so it seems to understand that a schematic should be in the same location as its corresponding symbol, but doesn't understand that symbols instanced in the schematic might also come from the same directory as the schematic. It appears that xschem has some built-in concept of "cwd" because if I don't put the current directory into the XSCHEM_LIBRARY_PATH (either as an absolute path from root or as

.

), then xschem will still find symbols in the directory where I start up. It doesn't seem like too much of a stretch to ask that the built-in concept of "cwd" should change to the directory where a schematic is being read, so that local files referenced by that schematic will be discovered automatically. Hopefully I explained that in an understandable way. . .

Hello everyone, I am currently going through various resources on SRAM design focusing on memory clock signal generation. I have found that most of the existing designs use external clock signal, and some designs use that external clock as a reference for internal clock generation. Most of the cases this external clk comes from the CPU. In our previous SRAM design, we have used external CLK from CPU, that means, we didn't need to work on CLK circuitry. Now, we want to design an on-memory CLK for the 32*1024 SRAM with the peripherals. Now, I wanted to seek your guidance on the necessity and feasibility of generating the clock signal entirely within the SRAM cell itself. Specifically, is it essential to find a method for internal clock generation within the SRAM? Or I also should follow the conventional approach to design internal clock generation circuit which will be engaged to generate clk for the memory but based on the external reference clk signal? Or Self-Timed (Asynchronous SRAM) approach should be followed? I would greatly appreciate your insights on this matter. Thank you so much in advance.

Script seems to work for metals, please check on your designs. 1. Update the variable

user_space

on the

main_*

functions to reflect the area of the chip. I'm testing without the padring. 2. Open the design on Klayout 3. Add script directory to Macro Development and execute it. (

Macros --> Macro Development --> Ruby --> Add Location

) I'm working on fix COMP errors now.

Hello everyone. I tried openlane + caravel flow with simple RTL. But 1 LVS error happened. Could you teach me the root cause and countermeasure? 〇Structure

• user_project_wrapper

+ user_project(Logic) + memory (sky130_sram_1kbyte_1rw1r_32x256_8) x 1 〇RTL

• user_project_wrapper has only connection.
• user_project has some small logic to write/read memory.

〇config - setting.png has json data. - user_project_wrapper and user_project RTL are synthesized simulteneously. 〇Error - LVS error happed in signoff phase. - They are in openlane.log.png and 29-lvs.lef.log.png.

@Tim Edwards When I tried to extract a spice file from a hierarchical circuit (integrator_circuit.png), I encountered an error stating, 'cannot read extract file sky130_fd_pr__pfet_01v8_M479BK.ext'. Do you have any suggestions for solving this problem? By the way, I did not encounter the error when performing extraction on a circuit with two inverters (two_inverters.pdf). Also, I have checked that LVS was OK for this two inverter circuit. Thanks in advance.

Might y’all know if there is a way to plot gm w/ this nested DC analysis that I am performing - or somehow plot the derivative of i(VD1) vs. Vgs w/ my current setup?