Hello everyone, I am currently going through various resources on SRAM design focusing on memory clock signal generation. I have found that most of the existing designs use external clock signal, and some designs use that external clock as a reference for internal clock generation. Most of the cases this external clk comes from the CPU. In our previous SRAM design, we have used external CLK from CPU, that means, we didn't need to work on CLK circuitry. Now, we want to design an on-memory CLK for the 32*1024 SRAM with the peripherals. Now, I wanted to seek your guidance on the necessity and feasibility of generating the clock signal entirely within the SRAM cell itself. Specifically, is it essential to find a method for internal clock generation within the SRAM? Or I also should follow the conventional approach to design internal clock generation circuit which will be engaged to generate clk for the memory but based on the external reference clk signal? Or Self-Timed (Asynchronous SRAM) approach should be followed? I would greatly appreciate your insights on this matter. Thank you so much in advance.

What frequency of clock are you trying to generate? The Caravel core has a synthesized ring oscillator that runs about 100MHz or so; the problem with this approach is that it is difficult to know what the frequency is going to be prior to synthesis, place, and route, and the frequency will vary by a factor of 2 over voltage and temperature corners. Any on-board oscillator will have the same variation unless it is part of a PLL and referenced to an external clock source.

Hi @Md. Sajjad Hossain I'm not sure if this applies, but 25 years ago asynchronous SRAM chips generated a precharge pulse based on address transition detection. They used this pulse to precharge bitlines, etc while the address was decoding.

Hello @Tim Edwards @David Lindley In our previous design, we controlled the word line, precharge/CLK, read enable, write enable using external signals. How can we control these functions from inside the memory using any block or circuitry that will also allow us to reduce the use of fewer external signals. Could you please help me with this please ?

I'm still not certain what you are asking. The 1kx32 SRAM has a defined set of interface signals. You must use them to access the RAM. Can you diagram what you are asking for to make the request clearer?

@David Lindley I was trying this way but is this one going in the right direction?