Hi, I just did a new project setup and tried running the user_project_example however its failing at STEP 9. During the build I see that the openroad process starts consuming all the system memory and my laptop becomes unresponsive, so I think the OS kills the process but I guess this should not be happening.

navaneeth@raptor:riscv_soc$ make user_proj_example
make -C openlane user_proj_example
make[1]: Entering directory '/home/navaneeth/.local/share/Trash/files/riscv_soc/openlane'
# user_proj_example
mkdir -p ./user_proj_example/runs/23_11_18_00_15 
rm -rf ./user_proj_example/runs/user_proj_example
ln -s $(realpath ./user_proj_example/runs/23_11_18_00_15) ./user_proj_example/runs/user_proj_example
docker run -it -u $(id -u $USER):$(id -g $USER) -v $(realpath /home/navaneeth/.local/share/Trash/files/riscv_soc/..):$(realpath /home/navaneeth/.local/share/Trash/files/riscv_soc/..) -v /home/navaneeth/asic/pdk:/home/navaneeth/asic/pdk -v /home/navaneeth/.local/share/Trash/files/riscv_soc/caravel:/home/navaneeth/.local/share/Trash/files/riscv_soc/caravel -v /home/navaneeth/asic/openlane:/openlane -v /home/navaneeth/.local/share/Trash/files/riscv_soc/mgmt_core_wrapper:/home/navaneeth/.local/share/Trash/files/riscv_soc/mgmt_core_wrapper -e PDK_ROOT=/home/navaneeth/asic/pdk -e PDK=gf180mcuC -e MISMATCHES_OK=1 -e CARAVEL_ROOT=/home/navaneeth/.local/share/Trash/files/riscv_soc/caravel -e OPENLANE_RUN_TAG=23_11_18_00_15 -e MCW_ROOT=/home/navaneeth/.local/share/Trash/files/riscv_soc/mgmt_core_wrapper  \
	efabless/openlane:2023.07.19-1 sh -c "flow.tcl -design $(realpath ./user_proj_example) -save_path $(realpath ..) -save -tag 23_11_18_00_15 -overwrite -ignore_mismatches"
OpenLane 30ee1388932eb55a89ad84ee43997bfe3a386421
(with mounted scripts from d054702b2cce04761cc2bc598f6b95c9d8ca7c6c)
All rights reserved. (c) 2020-2022 Efabless Corporation and contributors.
Available under the Apache License, version 2.0. See the LICENSE file for more details.

[INFO]: Using configuration in '../home/navaneeth/.local/share/Trash/files/riscv_soc/openlane/user_proj_example/config.json'...
[INFO]: PDK Root: /home/navaneeth/asic/pdk
[INFO]: Process Design Kit: gf180mcuC
[INFO]: Standard Cell Library: gf180mcu_fd_sc_mcu7t5v0
[INFO]: Optimization Standard Cell Library: gf180mcu_fd_sc_mcu7t5v0
[WARNING]: SYNTH_MAX_FANOUT is now deprecated; use MAX_FANOUT_CONSTRAINT instead.
[WARNING]: DIODE_INSERTION_STRATEGY is now deprecated; use GRT_REPAIR_ANTENNAS, DIODE_ON_PORTS and RUN_HEURISTIC_DIODE_INSERTION instead.
[INFO]: DIODE_INSERTION_STRATEGY set to 4. Setting RUN_HEURISTIC_DIODE_INSERTION to 1
[INFO]: DIODE_INSERTION_STRATEGY set to 4. Setting DIODE_ON_PORTS to in
[INFO]: Run Directory: /home/navaneeth/.local/share/Trash/files/riscv_soc/openlane/user_proj_example/runs/23_11_18_00_15
[INFO]: Saving runtime environment...
[INFO]: Preparing LEF files for the nom corner...
[INFO]: Preparing LEF files for the min corner...
[INFO]: Preparing LEF files for the max corner...
[WARNING]: PDK 'gf180mcuC', SCL 'gf180mcu_fd_sc_mcu7t5v0' will generate errors with instantiated stdcells in the design.
[WARNING]: Either disable QUIT_ON_LINTER_ERRORS or remove the instantiated cells.
[INFO]: Running linter (Verilator) (log: ../home/navaneeth/.local/share/Trash/files/riscv_soc/openlane/user_proj_example/runs/23_11_18_00_15/logs/synthesis/linter.log)...
[INFO]: 0 errors found by linter
[WARNING]: 9 warnings found by linter
[STEP 1]
[INFO]: Running Synthesis (log: ../home/navaneeth/.local/share/Trash/files/riscv_soc/openlane/user_proj_example/runs/23_11_18_00_15/logs/synthesis/1-synthesis.log)...
[STEP 2]
[INFO]: Running Single-Corner Static Timing Analysis (log: ../home/navaneeth/.local/share/Trash/files/riscv_soc/openlane/user_proj_example/runs/23_11_18_00_15/logs/synthesis/2-sta.log)...
[STEP 3]
[INFO]: Running Initial Floorplanning (log: ../home/navaneeth/.local/share/Trash/files/riscv_soc/openlane/user_proj_example/runs/23_11_18_00_15/logs/floorplan/3-initial_fp.log)...
[INFO]: Floorplanned with width 2786.56 and height 1724.8.
[STEP 4]
[INFO]: Running IO Placement (log: ../home/navaneeth/.local/share/Trash/files/riscv_soc/openlane/user_proj_example/runs/23_11_18_00_15/logs/floorplan/4-place_io.log)...
[STEP 5]
[INFO]: Running Tap/Decap Insertion (log: ../home/navaneeth/.local/share/Trash/files/riscv_soc/openlane/user_proj_example/runs/23_11_18_00_15/logs/floorplan/5-tap.log)...
[INFO]: Power planning with power {vccd1} and ground {vssd1}...
[STEP 6]
[INFO]: Generating PDN (log: ../home/navaneeth/.local/share/Trash/files/riscv_soc/openlane/user_proj_example/runs/23_11_18_00_15/logs/floorplan/6-pdn.log)...
[STEP 7]
[INFO]: Running Global Placement (log: ../home/navaneeth/.local/share/Trash/files/riscv_soc/openlane/user_proj_example/runs/23_11_18_00_15/logs/placement/7-global.log)...
[STEP 8]
[INFO]: Running Single-Corner Static Timing Analysis (log: ../home/navaneeth/.local/share/Trash/files/riscv_soc/openlane/user_proj_example/runs/23_11_18_00_15/logs/placement/8-gpl_sta.log)...
[STEP 9]
[INFO]: Running Placement Resizer Design Optimizations (log: ../home/navaneeth/.local/share/Trash/files/riscv_soc/openlane/user_proj_example/runs/23_11_18_00_15/logs/placement/9-resizer.log)...
[ERROR]: during executing openroad script /openlane/scripts/openroad/resizer.tcl
[ERROR]: Log: ../home/navaneeth/.local/share/Trash/files/riscv_soc/openlane/user_proj_example/runs/23_11_18_00_15/logs/placement/9-resizer.log
[ERROR]: Last 10 lines:
Using 1e+00 for voltage...
Using 1e-03 for current...
Using 1e-06 for power...
Using 1e-06 for distance...
Reading design constraints file at '/home/navaneeth/.local/share/Trash/files/riscv_soc/openlane/user_proj_example/runs/23_11_18_00_15/tmp/floorplan/3-initial_fp.sdc'…
[INFO]: Setting RC values...
[INFO RSZ-0027] Inserted 58 input buffers.
[INFO RSZ-0028] Inserted 65 output buffers.
[INFO RSZ-0058] Using max wire length 9189um.
child killed: kill signal

[ERROR]: Creating issue reproducible...
[INFO]: Saving runtime environment...
OpenLane TCL Issue Packager

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Parsing config file(s)…
Setting up /home/navaneeth/.local/share/Trash/files/riscv_soc/openlane/user_proj_example/runs/23_11_18_00_15/issue_reproducible…
[WRN] /home/navaneeth/.local/share/Trash/files/riscv_soc/openlane/user_proj_example/runs/23_11_18_00_15/tmp/placement/9-resizer.sdc was not found, might be a product. Skipping
Done.
[INFO]: Reproducible packaged: Please tarball and upload '../home/navaneeth/.local/share/Trash/files/riscv_soc/openlane/user_proj_example/runs/23_11_18_00_15/issue_reproducible' if you're going to submit an issue.
[ERROR]: Step 9 (placement) failed with error:
-code 1 -level 0 -errorcode NONE -errorinfo {
    while executing
"throw_error"
    (procedure "run_tcl_script" line 219)
    invoked from within
"run_tcl_script -tool openroad -no_consume {*}$args"
    (procedure "run_openroad_script" line 2)
    invoked from within
"run_openroad_script $::env(SCRIPTS_DIR)/openroad/resizer.tcl -indexed_log [index_file $::env(placement_logs)/resizer.log] -save "to=$::env(placement_t..."
    (procedure "run_resizer_design" line 8)
    invoked from within
"run_resizer_design"
    (procedure "run_placement" line 17)
    invoked from within
"run_placement"
    (procedure "run_placement_step" line 8)
    invoked from within
"run_placement_step"} -errorline 1
[INFO]: Saving current set of views in '../home/navaneeth/.local/share/Trash/files/riscv_soc/openlane/user_proj_example/runs/23_11_18_00_15/results/final'...
[INFO]: Generating final set of reports...
[INFO]: Created manufacturability report at '../home/navaneeth/.local/share/Trash/files/riscv_soc/openlane/user_proj_example/runs/23_11_18_00_15/reports/manufacturability.rpt'.
[INFO]: Created metrics report at '../home/navaneeth/.local/share/Trash/files/riscv_soc/openlane/user_proj_example/runs/23_11_18_00_15/reports/metrics.csv'.
[INFO]: Saving runtime environment...
[ERROR]: Flow failed.
[INFO]: The failure may have been because of the following warnings:
[WARNING]: PDK 'gf180mcuC', SCL 'gf180mcu_fd_sc_mcu7t5v0' will generate errors with instantiated stdcells in the design.
[WARNING]: Either disable QUIT_ON_LINTER_ERRORS or remove the instantiated cells.
[WARNING]: 9 warnings found by linter

make[1]: *** [Makefile:79: user_proj_example] Error 255
make[1]: Leaving directory '/home/navaneeth/.local/share/Trash/files/riscv_soc/openlane'
make: *** [Makefile:123: user_proj_example] Error 2

Any pointers is appreciated.

Hi! I have a question regarding the programming of the instruction memory used by the PicoRV32, we are trying to run the SoC on a ZedBoard FPGA for testing purposes since we also have our own added user components. We are using a wishbone bus for bus communication. I believe that memory is located not on the PicoRV32 but on the SoC in the SRAM, is there a way to program the SRAM through the ZedBoard's ARM processor (which is an AXI bus protocol) or to flash the SRAM using the QSPI flash interface? I have looked at the caravel_board and from what I am understanding, the way it programs the caravel processor is by flashing the caravel processor through SPI flash.

Hi everyone, so I am trying to do the parametric sweeping of NMOS to obtain its gm/id info across different L values. The entire netlist is as follows:

** sch_path: /fs1/eecg/tcc/lizongh2/gm_id/xschem/nfet_gm_id.sch
**.subckt nfet_gm_id
XM1 D G S S nfet_03v3 L=L_sweep W=W_sweep nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u'
+ pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W'
+ sa=0 sb=0 sd=0 m=M_sweep
Vg G S 1
.save i(vg)
Vd D S 1.65
.save i(vd)
**** begin user architecture code


.param W_sweep = 4u
.param L_sweep = 0.28u
.param M_sweep = 1

.control
.options savecurrents
set filetype=ascii

let L_start = 0.28u
let L_stop = 4u
let L_delta = 0.2u
let L_act = L_start

* loop
while L_act le L_stop
  alter @m.XM1.m0[l] = $&L_act
  reset
  dc Vg 0.3 3.3 0.3
  let gm = @m.XM1.m0[gm]
  let id = @m.XM1.m0[id]
  let gds = @m.XM1.m0[gds]
  let cgg = @m.XM1.m0[cgg]
  let vth = @m.XM1.m0[vth]
  let l = @m.XM1.m0[l]
  let w = @m.XM1.m0[w]
  print @m.XM1.m0[gm] @m.XM1.m0[l]
  remzerovec
  save all
  write nfet_gm_id.raw gm
  let L_act = L_act + L_delta
  set appendwrite
end

.endc



.include /usr/local/share/pdk/gf180mcuC/libs.tech/ngspice/design.ngspice
.lib /usr/local/share/pdk/gf180mcuC/libs.tech/ngspice/sm141064.ngspice typical

**** end user architecture code
**.ends
.GLOBAL GND
.end

However, I keep getting the following similar error:

Error: no model available for w=  4.0000000e-06 l=  6.8000000e-07.

Which I am not sure what causes this as the GF180MCU model is continuous. Any idea of this? Thanks.

Hello, I am trying to do a post implementation simulation but my design is failing the testbench. The output signals of my design are stuck at either 1 or X when using the post implementation netlist. The post synthesis netlist is behaving as expected. The design is implemented using openlane and sky130A technology (fd_sc_hd). The simulation is using the functional models of the standard cells. Does anyone have a suggestion for what could be causing this behavior? Thanks.

facing the following issue while doing

make setup

make[2]: Entering directory '/home/gsb/asic/openlane' Makefile23 warning: undefined variable 'DOCKER_SWAP' Makefile26 warning: undefined variable 'DOCKER_MEMORY' Makefile42 warning: undefined variable 'ROUTING_CORES' Makefile84 warning: undefined variable 'STD_CELL_LIBRARY' /bin/sh: 1: docker: not found make[2]: * [Makefile115 pull-openlane] Error 127 make[2]: Leaving directory '/home/gsb/asic/openlane' make[1]: * [Makefile90 openlane] Error 2 make[1]: Leaving directory '/home/gsb/AI_competition/ua/openlane' make: * [Makefile192 openlane] Error 2 how do i solve this?

This message contains interactive elements.

#Firesim_ChipYard Hi guys, I have a issue when run "firesim infrasetup" , follow up the guide at https://docs.fires.im/en/stable/Running-OnPrem-Simulations-Tutorial/Running-a-Single-Node-Simulation.html I faced a ERROR "fatal error: experimental/xrt_device.h: No such file or directory" It makes compilation terminate. | _fire/firesim/sim/output/vitis/FireSim-FireSimRocketMMIOOnlyConfig-BaseVitisConfig/build -std=c++17 -include /home/tonns/00_Chipyard/01_fire/firesim/sim/output/vitis/FireSim-FireSimRocketMMIOOnlyConfig-BaseVitisConfig/build/FireSim-generated.const.h -c -o /home/tonns/00_Chipyard/01_fire/firesim/sim/output/vitis/FireSim-FireSimRocketMMIOOnlyConfig-BaseVitisConfig/build/simif_vitis.o /home/tonns/00_Chipyard/01_fire/firesim/sim/midas/src/main/cc/simif_vitis.cc

2023-05-31 05:44:05,317 [flush       ] [INFO ]  [localhost] out:  [01m [K/home/tonns/00_Chipyard/01_fire/firesim/sim/midas/src/main/cc/simif_vitis.cc:12:10: [m [K  [01;31m [Kfatal error:  [m [Kexperimental/xrt_device.h: No such file or directory
2023-05-31 05:44:05,318 [flush       ] [INFO ]  [localhost] out:    12 | #include  [01;31m [K"experimental/xrt_device.h" [m [K
2023-05-31 05:44:05,318 [flush       ] [INFO ]  [localhost] out:       |           [01;31m [K^~~~~~~~~~~~~~~~~~~~~~~~~~~ [m [K
2023-05-31 05:44:05,318 [flush       ] [INFO ]  [localhost] out: compilation terminated.
2023-05-31 05:44:05,319 [flush       ] [INFO ]  [localhost] out: make[1]: *** [Makefile:45: /home/tonns/00_Chipyard/01_fire/firesim/sim/output/vitis/FireSim-FireSimRocketMMIOOnlyConfig-BaseVitisConfig/build/simif_vitis.o] Error 1
2023-05-31 05:44:05,319 [flush       ] [INFO ]  [localhost] out: make[1]: Leaving directory '/home/tonns/00_Chipyard/01_fire/firesim/sim/midas/src/main/cc'
2023-05-31 05:44:05,319 [flush       ] [INFO ]  [localhost] out: make: *** [make/driver.mk:44: /home/tonns/00_Chipyard/01_fire/firesim/sim/output/vitis/FireSim-FireSimRocketMMIOOnlyConfig-BaseVitisConfig/FireSim-vitis] Error 2
2023-05-31 05:44:05,321 [flush       ] [INFO ]  [localhost] out: 
2023-05-31 05:44:05,356 [flush       ] [INFO ]  Fatal error: run() received nonzero return code 2 while executing!
2023-05-31 05:44:05,356 [flush       ] [INFO ]  Requested: make DESIGN=FireSim TARGET_CONFIG=FireSimRocketMMIOOnlyConfig PLATFORM_CONFIG=BaseVitisConfig PLATFORM=vitis vitis
2023-05-31 05:44:05,356 [flush       ] [INFO ]  Executed: /bin/bash -l -c "cd /home/tonns/00_Chipyard/01_fire/firesim/deploy/../ && export RISCV=/home/tonns/00_Chipyard/01_fire/firesim/.conda-env/riscv-tools && export PATH=/home/tonns/00_Chipyard/01_fire/firesim/utils/fireperf:/home/tonns/00_Chipyard/01_fire/firesim/utils/fireperf/FlameGraph:/home/tonns/00_Chipyard/01_fire/firesim/sw/firesim-software:/home/tonns/00_Chipyard/01_fire/firesim/.conda-env/riscv-tools/bin:/home/tonns/00_Chipyard/chipyard/sims/1_fire/firesim/target-design/chipyard/software/firemarshal:/home/tonns/00_Chipyard/chipyard/sims/1_fire/firesim/target-design/chipyard/software/firemarshal:/home/tonns/00_Chipyard/chipyard/sims/1_fire/firesim/target-design/chipyard/software/firemarshal:/home/tonns/00_Chipyard/chipyard/sims/1_fire/firesim/target-design/chipyard/software/firemarshal:/home/tonns/00_Chipyard/chipyard/sims/1_fire/firesim/target-design/chipyard/software/firemarshal:/home/tonns/00_Chipyard/chipyard/sims/1_fire/firesim/target-design/chipyard/software/firemarshal:/home/tonns/00_Chipyard/chipyard/sims/1_fire/firesim/target-design/chipyard/software/firemarshal:/home/tonns/00_Chipyard/chipyard/sims/1_fire/firesim/target-design/chipyard/software/firemarshal:/home/tonns/00_Chipyard/chipyard/sims/1_fire/firesim/target-design/chipyard/software/firemarshal:/home/tonns/00_Chipyard/chipyard/sims/1_fire/firesim/target-design/chipyard/software/firemarshal:/home/tonns/00_Chipyard/chipyard/sims/1_fire/firesim/target-design/chipyard/software/firemarshal:/home/tonns/00_Chipyard/01_fire/firesim/.conda-env/bin:/opt/conda/condabin:/usr/local/bin:/usr/bin:/usr/local/sbin:/usr/sbin:/home/tonns/00_Chipyard/01_fire/firesim/deploy && export LD_LIBRARY_PATH=/home/tonns/00_Chipyard/01_fire/firesim/.conda-env/riscv-tools/lib && source sourceme-f1-manager.sh --skip-ssh-setup && cd sim/ && make DESIGN=FireSim TARGET_CONFIG=FireSimRocketMMIOOnlyConfig PLATFORM_CONFIG=BaseVitisConfig PLATFORM=vitis vitis"
2023-05-31 05:44:05,356 [flush       ] [INFO ]  Aborting.
2023-05-31 05:44:05,356 [<module>    ] [ERROR]  Fatal error.|

Please refer to the log file to know more information. Do you have any ideas to solve this problem? Best regards, TonNguyen

I had two problems while processing global placement of RePlAce. When I ran the global placement(GP) with the benchmark of ISPD 2015 contest, there were two benchmarks that could not process the GP stage smoothly. ( mgc_superblue16_a and mgc_superblue19 ) *benchmark of ISPD 2015 : https://www.ispd.cc/contests/15/web/downloads.html (Hidden benchmark designs ) I processed the following commands in my tcl file: read_lef {tech.lef} read_lef ${cells.lef} read_def ${floorplan.def} global_placement -density 1.0 After I processed benchmark of mgc_superblue19, the last 2 rows of error messages are: [NesterovSolve] Iter: 680 overflow: 0.18357 HPWL: 14598922301 [ERROR GPL-0307] RePlAce divergence detected. Re-run with a smaller max_phi_cof value. When I try smaller max_phi_cof value ( 1.1,1.3) with following command: global_placement -density 1.0 -max_phi_coef 1.03 There still had error message: [NesterovSolve] Iter: 680 overflow: 0.18357 HPWL: 14598922301 [ERROR GPL-0307] RePlAce divergence detected. Re-run with a smaller max_phi_cof value. And I further try smaller max_phi_cof global_placement -density 1.0 -max_phi_coef 1.01 The error will be solved, but the overflow will not decrease less than 0.1 after 5000 iterations of NesterovSolve. The last 2 rows of messages are: [NesterovSolve] Iter: 4990 overflow: 0.362241 HPWL: 12902711426 [NesterovSolve] Iter: 5000 overflow: 0.362278 HPWL: 12902395788 Another problem is that after I processing mgc_superblue16_a, the error message showed that : [ERROR GPL-0305] RePlAce diverged at newStepLength. But I have no idea how to solve this problem. Please help me, thanks!

Hi, I am running gate level simulation with sky130_fd_sc_hs, but i guess i lost this module "sky130_fd_sc_hs__u_vpwr_vgnd.v". Do you guys ever have a same issue? or any comments? thank you

I'm having an issue when trying to make caravel user_project_wrapper during Detailed Routing.

[ERROR DRT-0305] Net one_ of signal type POWER is not routable by TritonRoute. Move to special nets.

Error: droute.tcl, 46 DRT-0305

child process exited abnormally

What could be causing this error?