hey all, Has anyone else done some testing with the monte-carlo simulations (corner:mc)? I have been looking into this simulation, but when testing the current through a high poly resistor, I get a negative resistance for around 20% of the runs. When looking into this, I found the following: The SPICE file

libraries/sky130_fd_pr/latest/cells/res_xhigh_po/sky130_fd_pr__res_xhigh_po.model.spice

defines the resistor as R = R0 * (1 + var), with var being

sky130_fd_pr__res_xhigh_po__var_mult

defined in a comment in the file as a gaussian with std=0.025, but when looking at the netlist, the value is std=1.25*(0.0+agauss(0,1.0,1), or a gaussian with std=1.25. I believe this stems from another definition in

libraries/sky130_fd_pr/latest/models/parameters/montecarlo.spice

, where this var is defined as being 1.25 *

ic_res

. This

ic_res

is defined in

libraries/sky130_fd_pr/latest/models/parameters/critical.spice

as being 0.0. It also adds in comment that it should be a gaussian random variable with std=1. Does anyone have some more info on this? Cheers, Jelle

For Varactor, Xschem has three port (as attached). In magic its a PMOS. So, to make right connection in layout, which part of PMOS will be b, c0, c1 like in schematic? Thanks in advance!

Hi.. I was trying to import the sky130_fd_pr__nfet_03v3_nvt model spice file to layout. But I am getting guard rings for each standard cells. I can not remove the guard rings for each component. Is it necessary to keep guard rings for each component.? If not how can I remove that? I tried to draw it manually, but it is getting exported as 1.8v nfet spice file. I need 3.3v nfet. Please suggest a solution.

Hi, I am running gate level simulation with sky130_fd_sc_hs, but i guess i lost this module "sky130_fd_sc_hs__u_vpwr_vgnd.v". Do you guys ever have a same issue? or any comments? thank you

@Tim Edwards Hi We have the commercial SKY130 PDK in Cadence virtuoso . It has all the libraries the open source does except the RRAM. So I would like to ask if there is a way to include the RRAM library available in the open source PDK in Cadence. I know how to include the verilog-a model, but I am curious about its Layout files with DRC and LVS files. Also, the commercial PDK has only one pdk, it’s not divided into two sub pdks like the open source one SKY130A and SKY130B, any idea? Thanks

@Tim Edwards for some reason the

tt_mm

corner does not show any mismatch in devices. Below

test_comparator.sch

schematic, part of the

xschem_sky130

test circuits does not show any variation. The waveform is actually an overlay of 40 runs, they are all identical. It used to work in the past, showing differences in the output waveform per each run. The netlist calls the

sky130.lib.spice lib

with

tt_mm

corner. Do I need to set some switches or parameters? Netlist attached as well.

@User I see magic creates one more subckt level: one subckt for the inverter, one subcircuit for the P and N MOS transistors, finally containing the library transistor subcircuit call. xschem creates the subckt for the inverter with directly the library transistors subcircuit calls. I don't know if the extra hierarchy level creates a mismatch when doing LVS. Also the toplevel subcircuits (xschem and magic) have different port order. I don't know if the order of the i/o pins does matter.

What can be the reason for this

unknown subckt

error even though I have invoked the TT_MODELS ?

Hi, klayout "Trace All Nets" does not separate the terminals on mim caps. I don't know if klayout is capable of ignoring the conductivity of

M3-VIA3-M4

if

capm.drawing

layer is present (same principle for capm2). If that's possible, it would be very helpful. @Leo Moser @Tim Edwards. PD: Found a bug on file

sky130A.lyt

. On line 161 replace

met1='67/20...

with

li='67/20...

Need help with important information. Can we use BJTs in analog design in sky130 nm?