Hi All, after update/reinstall the open_pdk, and when try to simulate the reram_tb using ngspice I got the following errors: Note: Compatibility modes selected: hs a Error opening osdi lib "/home/eda_work/eman/hassan/share/pdk/sky130b/libs.tech/ngspice/sky130_fd_pr_reram__reram_module.osdi": No such file or directory! Error: Library /home/eda_work/eman/hassan/share/pdk/sky130b/libs.tech/ngspice/sky130_fd_pr_reram__reram_module.osdi couldn't be loaded! Circuit: ** sch_path: /home/eda_work/eman/hassan/share/pdk/sky130b/libs.tech/xschem/sky130_tests/tb_reram.sch Error on line: n.xr1.n1 top 0 xr1.nfilament sky130_fd_pr_reram__reram_model could not find a valid modelname Simulation interrupted due to error! any advice? @Stefan Schippers @Barak Hoffer @mkk @Tim Edwards

Do the corner simulations ss,ff,fs,sf model the resistor and cap variations with process.

Upto what frequency i.e. 5 , 10 or 20GHz can RFCMOS designs be done with open source sky130 PDK ? Are SPICE models available in sky130 PDK been characterized using S-parameter data ? As per foundry upto what max. frequency does these models support RF designs ?

Is it possible to run the OpenROAD gui inside the Openlane docker? When I try to do so I get the following error:

QStandardPaths: XDG_RUNTIME_DIR not set, defaulting to '/tmp/runtime-'
process 9: The last reference on a connection was dropped without closing the connection. This is a bug in an application. See dbus_connection_unref() documentation for details.
Most likely, the application was supposed to call dbus_connection_close(), since this is a private connection.
  D-Bus not built with -rdynamic so unable to print a backtrace
Stack trace:
 0# 0x0000000001035AA6 in openroad
 1# 0x00007F16C53C4400 in /lib64/libc.so.6
 2# gsignal in /lib64/libc.so.6
 3# abort in /lib64/libc.so.6
 4# 0x00007F16BA845655 in /lib64/libdbus-1.so.3
 5# _dbus_warn_check_failed in /lib64/libdbus-1.so.3
 6# 0x00007F16BDAFCBFB in /lib64/libQt5DBus.so.5
 7# QObject::event(QEvent*) in /lib64/libQt5Core.so.5
 8# 0x00007F16C66F5A55 in /lib64/libQt5Core.so.5
 9# QCoreApplication::notifyInternal2(QObject*, QEvent*) in /lib64/libQt5Core.so.5
10# QCoreApplicationPrivate::sendPostedEvents(QObject*, int, QThreadData*) in /lib64/libQt5Core.so.5
11# 0x00007F16C6744A03 in /lib64/libQt5Core.so.5
12# g_main_context_dispatch in /lib64/libglib-2.0.so.0
13# 0x00007F16C235C3F8 in /lib64/libglib-2.0.so.0
14# g_main_context_iteration in /lib64/libglib-2.0.so.0
15# QEventDispatcherGlib::processEvents(QFlags<QEventLoop::ProcessEventsFlag>) in /lib64/libQt5Core.so.5
16# QEventLoop::exec(QFlags<QEventLoop::ProcessEventsFlag>) in /lib64/libQt5Core.so.5
17# QThread::exec() in /lib64/libQt5Core.so.5
18# 0x00007F16BDAFA3B5 in /lib64/libQt5DBus.so.5
19# 0x00007F16C654BE71 in /lib64/libQt5Core.so.5
20# 0x00007F16C810EEA5 in /lib64/libpthread.so.0
21# clone in /lib64/libc.so.6
QThread::wait: Thread tried to wait on itself
QMutex: destroying locked mutex
QThread: Destroyed while thread is still running
Stack trace:
 0# 0x0000000001035AA6 in openroad
 1# 0x00007F16C53C4400 in /lib64/libc.so.6
 2# gsignal in /lib64/libc.so.6
 3# abort in /lib64/libc.so.6
 4# 0x00007F16C6538CE1 in /lib64/libQt5Core.so.5
 5# QThread::~QThread() in /lib64/libQt5Core.so.5
 6# 0x00007F16BDAFA5D9 in /lib64/libQt5DBus.so.5
 7# 0x00007F16C53C7CE9 in /lib64/libc.so.6
 8# 0x00007F16C53C7D37 in /lib64/libc.so.6
 9# 0x0000000001035ACB in openroad
10# 0x00007F16C53C4400 in /lib64/libc.so.6
11# gsignal in /lib64/libc.so.6
12# abort in /lib64/libc.so.6
13# 0x00007F16BA845655 in /lib64/libdbus-1.so.3
14# _dbus_warn_check_failed in /lib64/libdbus-1.so.3
15# 0x00007F16BDAFCBFB in /lib64/libQt5DBus.so.5
16# QObject::event(QEvent*) in /lib64/libQt5Core.so.5
17# 0x00007F16C66F5A55 in /lib64/libQt5Core.so.5
18# QCoreApplication::notifyInternal2(QObject*, QEvent*) in /lib64/libQt5Core.so.5
19# QCoreApplicationPrivate::sendPostedEvents(QObject*, int, QThreadData*) in /lib64/libQt5Core.so.5
20# 0x00007F16C6744A03 in /lib64/libQt5Core.so.5
21# g_main_context_dispatch in /lib64/libglib-2.0.so.0
22# 0x00007F16C235C3F8 in /lib64/libglib-2.0.so.0
23# g_main_context_iteration in /lib64/libglib-2.0.so.0
24# QEventDispatcherGlib::processEvents(QFlags<QEventLoop::ProcessEventsFlag>) in /lib64/libQt5Core.so.5
25# QEventLoop::exec(QFlags<QEventLoop::ProcessEventsFlag>) in /lib64/libQt5Core.so.5
26# QThread::exec() in /lib64/libQt5Core.so.5
27# 0x00007F16BDAFA3B5 in /lib64/libQt5DBus.so.5
28# 0x00007F16C654BE71 in /lib64/libQt5Core.so.5
29# 0x00007F16C810EEA5 in /lib64/libpthread.so.0
30# clone in /lib64/libc.so.6

Hi, I got this error "Can't open ABC output file" when running "abc -liberty cells.lib" on Yosys. Is it because of using "cells.lib"? How to fix it? When I run it directly after "read_verilog" before "synth -top" I got "skipping model as it contains processes" I can't understand it, any explanation, please? What is the command to download libs (sk130) I only have "cells.lib", please?

Hi, I run into an error below while trying to run iverilog simulation, /caravel_user_project/caravel/verilog/rtl/caravel_netlists.v41 Include file libs.ref/sky130_fd_io/verilog/sky130_ef_io.v not found is it due to wrong versioning of pdk? I installed openlane and built pdks via openlane repository

I'm trying the sky130 support in OpenRAM, using the example config

./compiler/example_configs/riscv_sky130_1kbyte_1rw1r.py

(PS: the 1r1w variants don't work)

magic

segfaults during execution of

run_ext.sh

and therefore no spice file is generated:

Extracting sram_1rw1r0w_32_256_sky130 into sram_1rw1r0w_32_256_sky130.ext:
Total of 5 warnings.
Finished extract
./run_ext.sh: line 38: 21392 Segmentation fault: 11  /usr/local/bin/magic -dnull -noconsole  <<EOF

I'm trying to debug that, but I'm also getting some error messages which I don't know if they should be of any concern or not. For example:

Error:  Asymmetric device with multiple terminals!

I need to create my own digital PLL to achieve higher frequencies than the base 50MHz system clock. Following the model in the caravel repo I get

ERROR: Module `\sky130_fd_sc_hd__einvn_8' referenced in module `\delay_stage' in cell `\delayenb0' is not part of the design.

The component exists, why can't I use it?

I'm trying to simulate an extracted spice netlist of about 50 cells. I'm trying for 5 clock cycles over 20ns. It's taking forever! Are there any techniques to speed up spice simulation of larger designs?

If you want to use gaw (https://github.com/StefanSchippers/xschem-gaw) ensure the ~/.gaw/gawrc contains the line:

up_listenPort = 2020

Ensure the ~/.xschem/xschemrc contains the line:

set gaw_tcp_address {localhost 2020}

A better option is to view data directly into xschem: https://xschem.sourceforge.io/stefan/xschem_man/graphs.html#graphs