I need to create my own digital PLL to achieve higher frequencies than the base 50MHz system clock. ...

Jean

10/24/2021, 2:32 AM

I need to create my own digital PLL to achieve higher frequencies than the base 50MHz system clock. Following the model in the caravel repo I get

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ERROR: Module `\sky130_fd_sc_hd__einvn_8' referenced in module `\delay_stage' in cell `\delayenb0' is not part of the design.

The component exists, why can't I use it?

Mitch Bailey

10/24/2021, 9:51 PM

@User This may be a really dumb suggestion, but is the back slash in the module name supposed to be there?

Jean

10/25/2021, 1:46 PM

The backslash isn't there in the verilog code, only in the error message

Mitch Bailey

10/25/2021, 5:03 PM

@User Are you able to post your verilog code? Your

STD_CELL_LIBRARY

is set to

sky130_fd_sc_hd

, correct?

Jean

10/26/2021, 4:48 AM

Yes STD_CELL_LIBRARY is set, and the code is simply a clone of the ring oscillator code from the caravel harness.

Mitch Bailey

10/26/2021, 5:00 AM

What version of openlane?

Mitch Bailey

10/26/2021, 5:11 AM

FWIW, I ran a copy of

digital_pll

on openlane

2021.09.30_02.12.16

and ran into an undefined clock error.

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create_clock [get_ports $::env(CLOCK_PORT)] -name $::env(CLOCK_PORT) -period $::env(CLOCK_PERIOD)
Error: base.sdc, 1 can't read "::env(CLOCK_PORT)": no such variable

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