Greetings, So I am designing a simple LDO with sky130 technology (I know there are already some designs out there on GitHub but they either actually have some issues or do not meet my design requirements). And I am having some problems with the PSRR performance of the LDO. The first schematic below is my error amp for now which is a simple active load diff pair. The second schematic is the LDO itself. The third schematic is the testbench for LDO. For this design, Vdd is set to 2V and Vreg is set to 1.8V. Assuming I have a Vref of 1.8V, so there is no resistive divider here. I am targeting at this point a minimum load current of 100uA and a maximum load current of 10mA. Now I am trying to do the loop-gain analysis in Ngspice (which is the main issue of many designs out there as their loop stability analysis is problematic). Here I have done three different loop-stability analyses: Ochoa's Z method, Middlebrook's method, and Tian's method. The fourth schematic shows the testbench for Ochoa's Z method, and the fifth schematic shows the testbench for Middlebrook's and Tian's method (same testbench but different way of calculations). Just in case if you are curious of how these methods are done, please see the following: Ochoa's Z method: Middlebrook's and Tian's method: http://education.ingenazure.com/ac-stability-analysis-ngspice/ (It is also theoretically possible of doing big cap/ind method as described here: https://www.eecg.toronto.edu/~johns/ece331/lecture_notes/22_LG_simulation.pdf but there are some convergence issue with big cap/ind values in Ngspice so I did not use this method here) I have to note here that all these methods do not disturb DC biasing point, and are taking the loading effect into account. Anyway, I obtained fairly similar results for these method for the loop-gain Bode plot with a load current of 100uA, which I have only shown the Middlebrook's result in the sixth figure, which I understand that the phase margin is pretty bad (as I have not optimized my design yet). It has a DC gain of about 50dB and an unity-gain frequency of 1MHz. And now here is the problem. It is well-established that the PSRR of LDO, before the unity-gain frequency, is approximately equal to 1/L where L is the loop-gain. This means that I should expect a PSRR of around -50dB at DC and start to deteriorate around the unity-gain frequency (and the output decap starts to kick in at high frequency). But the simulation result of the PSRR is not what I expected, which is shown in the seventh schematic, and I am not very sure what causes this. Any insight to this will be extremely helpful!

Hi, I am about to put a VCO analog circuit into caravel for MPW5 tapeout. However, my VCO has an analog port "Vctrl" which is supposed to take in an analog voltage (anything between 0.4V up to 1.3V approx) in order to generate an output frequency that is proportional to this Vctrl. My question is, does Caravel have Analog input pins at all, or just digital? Thanks

Hi, I was able to import the spice file before with the loaded sky130A.tech file and sky130A.magicrc file, but I did not save it because I wanted to have a clean import again. However, now when I import the spice file into magic, it says that it cannot find the MOSFETs I was using previously. Is the library parth for the devices done in the rc file or the tech file? Sorry if it's very vague description of what caused the problem.

Hi everyone. According to the file caravel_user_project_analog/xschem/analog_wrapper_tb.spice. I can do simulation with the wrapper. Is there any method to run the simulation with pad?

I am using sky130 libraries and facing the following issue. I wrote the RTL for a simple DFF and synthesized it and ran the GLS on the netlist. The verilog model of the flop in sky130 lib seems to be wrong and i am seeing q pin to be floating in the GLS output. This is because the verilog model is using some signals *_DELAYED (like D_DELAYED , RESET_B_DELAYED, etc) in it which are not driven inside the model. Have posted the snippet of the model along with this post. Please share me if you are aware of any known workarounds / limitations . Thanks in advance for help._

is there any neat way to stop openroad from trying to place all of the logic in the small gap between macros rather than in the bigger area away from the macros? neither of the halo options seem to affect this even though they seem like a conceptually similar problem

Hi all. I have downloaded openlane2 as per https://openlane2.readthedocs.io/en/latest/getting_started/common/nix_installation/installation_linux.html. I then try to run an example using: openlane --run-example spm After this it errors out with the following message: PermissionError: [Errno 13] Permission denied: '/home/slice/pdk/SW130/share/pdk/volare' This is most probably due to the fact I havent used volare to install my pdk. Instead it is installed at: /home/slice/pdk/SW130/share/pdk/sky130A I guess I just have to change a pointer to this above path? Is this correct? If so, how do I proceed? Thanks, Diarmuid

Could I get some help in configuring the GPIO in openframe projects for analog signalling? Reading the docs here, it seems to me I have to do a combination of configure the drive mode to 000, and something involving the analog_en, pol, and sel signals. But, this diagram here suggests to me that maybe pad_a_noesd_h is the same as analog_noesd_io (and analog_io the same as pad_a_esd)? and thus, we don't need to configure anything else to be able to use the pads? (other than oeb)

I wonder if anyone has figured out the following for ngspice: Run a transient analysis up to some time, save the circuit state, then use that state as the operating point for subsequent ac, noise, etc. analyses. This is frequently needed for SC circuits that need a few clock cycles to initialize, and it is supported by proprietary tools like spectre. For ngspice, I could find the thread linked below, where the question it asked at the bottom, but not answered. (I have been trying optran, but it seems that it is not meant to do what I am asking for.) https://sourceforge.net/p/ngspice/discussion/127605/thread/ca4d596065/

Hi All, after update/reinstall the open_pdk, and when try to simulate the reram_tb using ngspice I got the following errors: Note: Compatibility modes selected: hs a Error opening osdi lib "/home/eda_work/eman/hassan/share/pdk/sky130b/libs.tech/ngspice/sky130_fd_pr_reram__reram_module.osdi": No such file or directory! Error: Library /home/eda_work/eman/hassan/share/pdk/sky130b/libs.tech/ngspice/sky130_fd_pr_reram__reram_module.osdi couldn't be loaded! Circuit: ** sch_path: /home/eda_work/eman/hassan/share/pdk/sky130b/libs.tech/xschem/sky130_tests/tb_reram.sch Error on line: n.xr1.n1 top 0 xr1.nfilament sky130_fd_pr_reram__reram_model could not find a valid modelname Simulation interrupted due to error! any advice? @Stefan Schippers @Barak Hoffer @mkk @Tim Edwards