Hi everyone, so I am trying to do the parametric sweeping of NMOS to obtain its gm/id info across different L values. The entire netlist is as follows:

** sch_path: /fs1/eecg/tcc/lizongh2/gm_id/xschem/nfet_gm_id.sch
**.subckt nfet_gm_id
XM1 D G S S nfet_03v3 L=L_sweep W=W_sweep nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u'
+ pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W'
+ sa=0 sb=0 sd=0 m=M_sweep
Vg G S 1
.save i(vg)
Vd D S 1.65
.save i(vd)
**** begin user architecture code


.param W_sweep = 4u
.param L_sweep = 0.28u
.param M_sweep = 1

.control
.options savecurrents
set filetype=ascii

let L_start = 0.28u
let L_stop = 4u
let L_delta = 0.2u
let L_act = L_start

* loop
while L_act le L_stop
  alter @m.XM1.m0[l] = $&L_act
  reset
  dc Vg 0.3 3.3 0.3
  let gm = @m.XM1.m0[gm]
  let id = @m.XM1.m0[id]
  let gds = @m.XM1.m0[gds]
  let cgg = @m.XM1.m0[cgg]
  let vth = @m.XM1.m0[vth]
  let l = @m.XM1.m0[l]
  let w = @m.XM1.m0[w]
  print @m.XM1.m0[gm] @m.XM1.m0[l]
  remzerovec
  save all
  write nfet_gm_id.raw gm
  let L_act = L_act + L_delta
  set appendwrite
end

.endc



.include /usr/local/share/pdk/gf180mcuC/libs.tech/ngspice/design.ngspice
.lib /usr/local/share/pdk/gf180mcuC/libs.tech/ngspice/sm141064.ngspice typical

**** end user architecture code
**.ends
.GLOBAL GND
.end

However, I keep getting the following similar error:

Error: no model available for w=  4.0000000e-06 l=  6.8000000e-07.

Which I am not sure what causes this as the GF180MCU model is continuous. Any idea of this? Thanks.

Hi all, I'm trying to simulate a ring oscillator in xschem (actually ngspice). In the ngspice console, I get:

Checking parameters for BSIM 4.5 model x3.xm1:sky130_fd_pr__nfet_01v8__model.25
Fatal: Pclm = -0.0968433 is not positive.
Fatal: Drout = -0.261499 is negative.
Warning: Cdscd = -0.00649389 is negative.
Warning: Eta0 = -0.0934787 is negative.
Fatal error: detected during BSIM4v5.5.0 parameter checking for 
    model x3.xm1:sky130_fd_pr__nfet_01v8__model.25 of device instance m.x3.xm1.msky130_fd_pr__nfet_01v8

I've tried 1 inverter and 3 inverters. I'm attaching PNG exports from xschem. Any advice appreciated.

You can use set_max_delay for that. However, if you use it to constraint logic that has other larger paths going through it, those will be broken. It would be best to do report_check -through a_in -through a_out and see the full path. If that constrant can be adjusted its best. If the path is unconstrainted you should figure out why but can use the set_max_delay without fear of unconstraining constrained paths.

@Stefan Schippers also for pulse waveform which one to use ? Or we use the vsource and edit the voltages as : PULSE ( V1 V2 TD TR TF PW PER PHASE )

Is there a way to parse the spice files and get metadata? Some ngspice command or something, or maybe even PySpice.

On the xschem_sky130 nfet and pfet symbols, it might be nice if the gate and backgate pins were not at the same y-coordinate, so that in a current mirror with many outputs, the gates of many fets could all be connected together by a single horizontal wire and likewise the backgates could all be connected together with another horizontal wire. (If there are models for nmos inside p-well inside n-well in the substrate, with the wells all brought to pins on the symbol, then ideally each of these pins would be drawn at different y-coordinates.) As changing the symbols would break people's schematics, I'm not sure how it would be best to manage the change - provide them as alternative symbols only for new designs perhaps. Also I think res_generic_po symbol shouldn't have diodes shown on it, if it is a poly resistor.

@Stefan Schippers is it possible in xschem to parameterize component vectors and busses to change the number of elements? I've been playing with a chain of resistors to give me a more accurate model that includes the contact effects when building a large resistor out of smaller parts (see attached). It would be great if this could be made into a more parameterized symbol that can be re-used for arbitrary chain lengths.

Is it possible to use the NCSU Freepdks with FOSS tools like Xschem? I was looking for a Free PDK with around 40nm channel length for an academic project, it was the only one I could find.

Hello all, I'm trying to achieve LVS match of the two netlists attached using netgen, without success... my first time doing manual layout with standard cells, so no idea if anythign special should be done - for example it mentions black boxes, no idea if this is as it should be:

Circuit 1 cell sky130_fd_sc_hd__clkdlybuf4s50_2 is a black box; will not flatten Circuit 2

Warning: Equate pins:  cell sky130_fd_sc_hd__clkdlybuf4s50_2 is a placeholder, treated as a black box.

I'm working on the IIC-OSIC tools docker, with the following command: "netgen -batch lvs "/foss/designs/Open3LFCC_V2_GD12V/LS_boot_20230921/sch/sp_delay_sch.spice sp_delay" "/foss/designs/Open3LFCC_V2_GD12V/magic/tcl/sp_delay_lyt.spice sp_delay" /foss/pdks/sky130A/libs.tech/netgen/sky130A_setup.tcl lvs_delay.log" I'm attaching below the .log file in case anyone can take a look, any help would be greatly appreciated!

Hi! I have a question regarding the programming of the instruction memory used by the PicoRV32, we are trying to run the SoC on a ZedBoard FPGA for testing purposes since we also have our own added user components. We are using a wishbone bus for bus communication. I believe that memory is located not on the PicoRV32 but on the SoC in the SRAM, is there a way to program the SRAM through the ZedBoard's ARM processor (which is an AXI bus protocol) or to flash the SRAM using the QSPI flash interface? I have looked at the caravel_board and from what I am understanding, the way it programs the caravel processor is by flashing the caravel processor through SPI flash.