Is there a list somewhere of all available TCL commands ? I need to find an instance name from a "glob". ( actual instance name is something like

gpio\[0\].gpio_I.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.pad_I

) but I'd like to find the complete name using just the prefix

gpio\[0\]

.

hey all, Has anyone else done some testing with the monte-carlo simulations (corner:mc)? I have been looking into this simulation, but when testing the current through a high poly resistor, I get a negative resistance for around 20% of the runs. When looking into this, I found the following: The SPICE file

libraries/sky130_fd_pr/latest/cells/res_xhigh_po/sky130_fd_pr__res_xhigh_po.model.spice

defines the resistor as R = R0 * (1 + var), with var being

sky130_fd_pr__res_xhigh_po__var_mult

defined in a comment in the file as a gaussian with std=0.025, but when looking at the netlist, the value is std=1.25*(0.0+agauss(0,1.0,1), or a gaussian with std=1.25. I believe this stems from another definition in

libraries/sky130_fd_pr/latest/models/parameters/montecarlo.spice

, where this var is defined as being 1.25 *

ic_res

. This

ic_res

is defined in

libraries/sky130_fd_pr/latest/models/parameters/critical.spice

as being 0.0. It also adds in comment that it should be a gaussian random variable with std=1. Does anyone have some more info on this? Cheers, Jelle

How do I find a list of properties for a particular object that can be accessed with get_property? For example, if I have a pin, what properties are there for a pin? Location?

Hi there, I cant seem to find the answers to the following questions online (perhaps I don't know what to search for... 1. Once I've launched openlane I cannot access folders outside the environment created by openlane, how do I fix this so I can access files in my project work area without having to copy them into openlane's design folder every time 2. I don't seem to be able to get openlane to use the PDKs that I have installed separately without getting errors from

make mount

3. Once synthesizing a design openlane always breaks-out the designs pins with long wires extended outside the boundary of the hardened block. How do I prevent this from happening and instead just get it to place ports within the design boundary to which I can connect Thanks in anticipation, Tom

I have a question about generating the power grid through openlane. I have to bring in analog blackboxes that use mimcaps through m3-m5 so I can't have the PDN grid cover the entire chip. I tried metal obstructions but since the PDN gets generated first, I am trying to keep the grid out of the analog area with halos:

set ::env(FP_PDN_HORIZONTAL_HALO) 420

set ::env(FP_PDN_VERTICAL_HALO) 420

But I am not quite sure how this works...the horizontal power straps persist. Is there to disable both horizontal and vertical stripes in the halo area?

Hi All, I am new user to the Sky130 open-source and I am trying to get my CAD tool environment setup correctly. I set up my first simulations following some of the tutorials. The problem I have is with the simulation control window Font Size. The Fonts are too small to read. What configuration file do I need to edit in order to increase the size of the Fonts in the "simulation control" window. The attached file is a screen snap shot of my xschem window, the simulation control window, and the waveform viewer window. The simulation control window is the top left window on the screen snap shot image

Does anyone know a tool that can generate/extract LEF from GDS?

Hi , my design is failing in detailed routing step.. Logfile doesnt seem to contain info for debug: [INFO]: Running Global Routing... [INFO]: Starting FastRoute Antenna Repair Iterations... [STEP 19] [INFO]: Running Fill Insertion... [STEP 20] [INFO]: Writing Verilog... [STEP 21] [INFO]: Running Detailed Routing... [ERROR]: during executing openroad script /openlane/scripts/openroad/droute.tcl [ERROR]: Exit code: 1 [ERROR]: full log: designs/counter/runs/RUN_2022.08.05_14.23.00/logs/routing/21-detailed.log [ERROR]: Last 10 lines: [INFO DRT-0181] Start track assignment. [INFO DRT-0184] Done with 308 vertical wires in 15 frboxes and 215 horizontal wires in 15 frboxes. [INFO DRT-0186] Done with 8 vertical wires in 15 frboxes and 24 horizontal wires in 15 frboxes. [INFO DRT-0182] Complete track assignment. [INFO DRT-0267] cpu time = 000352, elapsed time = 000206, memory = 9151.66 (MB), peak = 11359.00 (MB) [INFO DRT-0187] Start routing data preparation. [INFO DRT-0267] cpu time = 000000, elapsed time = 000000, memory = 9151.72 (MB), peak = 11359.00 (MB) [INFO DRT-0194] Start detail routing. [INFO DRT-0195] Start 0th optimization iteration. child killed: kill signal [INFO]: Saving runtime environment... [INFO]: Creating reproducible... How can i log a case ? I forgot the steps

Hmm, does anyone have had experience with dealing with errors of the type

[ERROR]: There are illegal overlaps (e.g., routes over obstructions) in your design.

[ERROR]: See /path/to/project/openlane/user_project_wrapper/runs/user_project_wrapper/logs/finishing/27-ext2spice.feedback.txt for more.

at the last steps of the overall hardening flow (for the wrapper)? The said file contains many lines of the following form:

box 80124 41296 80875 41347

feedback add "Illegal overlap between obsm1 and metal1 (types do not connect)" medium

When looking at the generated gds file in klayout, depending on the unit used in that the feedback.txt file, either there is nothing at that place, or the position is inside an SRAM macro. What would make sense to look for for fixing the problem(s)?

Is it possible to do MEMS design with the Sky130 PDK and Magic/Klayout? Looking at the fact that only regular shapes are allowed in both these tools, I think that the answer is going to be no.