error_dc_reram.PNG

My server has 48 cores, currently openlane only uses a maximum of 1 core to run, resulting in the running process being very slow. Is there any way to take full advantage of CPU cores to run openlane?

Hello, I am trying to do a post implementation simulation but my design is failing the testbench. The output signals of my design are stuck at either 1 or X when using the post implementation netlist. The post synthesis netlist is behaving as expected. The design is implemented using openlane and sky130A technology (fd_sc_hd). The simulation is using the functional models of the standard cells. Does anyone have a suggestion for what could be causing this behavior? Thanks.

Hi , i have created a verilog wrapper file with my analog macro inside it...And in the openlane i am feeding the LEF , LIB and GDS....But flow errors out... The LEF is written from magic. What i suspect is that the tool is not able to TAP the pin Any guidelines on how to create pins of the macros ?? particular width / hegith needed ?? LMK what are all info /files required [STEP 19] [INFO]: Running Global Routing... [INFO]: Starting FastRoute Antenna Repair Iterations... [STEP 20] [INFO]: Running Fill Insertion... [STEP 21] [INFO]: Writing Verilog... [STEP 22] [INFO]: Running Detailed Routing... [ERROR]: during executing openroad script /openlane/scripts/openroad/droute.tcl [ERROR]: Exit code: 1 [ERROR]: full log: designs/AMUX_wrapper/runs/RUN_2022.08.28_12.23.54/logs/routing/22-detailed.log [ERROR]: Last 10 lines: [INFO DRT-0033] via2 shape region query size = 1920. [INFO DRT-0033] met3 shape region query size = 1454. [INFO DRT-0033] via3 shape region query size = 1920. [INFO DRT-0033] met4 shape region query size = 511. [INFO DRT-0033] via4 shape region query size = 16. [INFO DRT-0033] met5 shape region query size = 26. [INFO DRT-0165] Start pin access. [ERROR DRT-0073] No access point for U_AMUX_8x1_20_08_layout/V4. Error: droute.tcl, 46 DRT-0073 child process exited abnormally

I am running OpenLane without Docker since I'm doing mostly analog design. When I try to run "./flow.tcl -design spm" I get the following error: "[ERROR STA-0402] repair_design -slew_margin is not a known keyword or flag. Error: resizer.tcl, 62 STA-0402 [ERROR]: during executing: "openroad -exit /mnt/HDD_WD/OpenLane/scripts/openroad/resizer.tcl |& tee >&@stdout /mnt/HDD_WD/OpenLane/designs/spm/runs/RUN_2021.12.12_15.55.21/logs/placement/8-resizer.log" [ERROR]: Exit code: 1 [ERROR]: Last 10 lines: child process exited abnormally" I'm running Version: 2021.12.10_01.41.40 All the fixes I found here were for the docker image, does anybody have the fix for the setup without it?

Has anyone encountered any of the following errors when reading a GDS in Magic? (1) Don't know how to read `GDS-II`: Nothing in "`cifinput`" section of tech file (2) Can not find channel named "`gds`"

Released xschem 3.4.6

Hi, I'm getting the an error on step 15 "Running Global Routing Resizer Design Optimizations" while trying to harden my custom user_proj_example with Caravel (please let me know if this question is more relevant for #C01EX4ATEKF). I'm pasting the output of

make user_proj_example

. https://pastebin.com/BE2Vn1MC Please let me know if any other logs are needed. Here's `15-resizer_design.log`: https://pastebin.com/JJAcQNfP

Hello, I am following the "Open Source Analog Design Flow" document to build Xyce which depends on Trilinos. I follow the instructions to build a parallel version of Trilinos which builds fine but when I attempt to configure Xyce it complains with:

checking for Teuchos_SerialDenseMatrix.hpp... no
configure: error: Unable to compile a test program against Trilinos that includes Teuchos_Serial_DenseMatrix.hpp.  It is possible Trilinos was not properly configured or the environment has changed since Trilinos was installed.  See config.log for more information.

I seem to recall that when I last built Xyce I had to resort to a serial build (the clue is in the name of the missing file) unless that's a false memory. Any ideas on what might be wrong given I follow the recipe precisely?

anyone has an idea of the cost of a full mask for the SKY130 process? I heard 130nm processes are normally about $60k per masks. Can someone confirm? Anyone also knows the cost of a wafer?