I'm trying to run the static timing analysis on the caravel design including our user project area. Right now I'm only focusing on the main clock (no other external IO or reset yet), and just using the modules:

caravel

,

mgmt_core

,

mgmt_protect

, and a "fake"

chip_io

that just forwards clock to clock_core My idea is first check if the wishbone bus and LA meet the timings Here is the WIP repository of the project: https://github.com/mbalestrini/caravel_timing_analysis On the first tests I'm getting HOLD violations between mgmt_core and our user_project_wrapper and it seems I'm also getting HOLD violations inside mgmt_core. If anyone with more experience wants to check the repository to see if the process is correct or if I'm missing something that would be great. (I'm using caravel's mpw-3a tag)

Hello everyone. I am working on an open source wire bonding application for QFN packages, although the algorithm I constructed can be generalized for all sorts of packages. I was wondering if anyone has experience using proprietary software, so I have something to compare it with.

Hello! I would like to run a simulation with Verilator+Cocotb, generate a VCD, then perform power analysis on that VCD. Does anyone know of a good flow for this? • I see report_power from OpenSTA, but that's just static analysis: https://github.com/The-OpenROAD-Project/OpenSTA/blob/1c7f022c/doc/ChangeLog.txt#L106-L126 • Vivado can do power analysis only on SAIF files, not VCD files. I see Synopsys's vcd2saif online, but no free/open-source solutions • Can I synthesize for sky130, then run ngspice to match my VCD somehow? (I feel like that is overkill though) Thanks in advance!

Hi, I'm having problems installing klive.

Error 0: Request creation failed, fetching <http://sami.klayout.org/repository.xml>

The file is online and I'm running klayout on a docker container. Does anyone has this error and solve it?

Out of curiosity, is there any downside to using LVT devices compared to standard devices? From an analog POV, I only see benefits from LVT devices: lower threshold -> lower overdrive -> better swing.

How can I generate a pad frame around my design in order to perform full chip simulation?

Hello All, I'm struggling a bit with the analog layout using magic, I found two approaches: 1. Draw poligons from scratch as in BMINCH's youtube tutorials (e.g.

https://www.youtube.com/watch?v=RPppaGdjbj0▾

https://www.youtube.com/watch?v=RPppaGdjbj0

) a. The main pros are that you get to understand pretty well the layer configuration and make sense of your layout for possible optimization b. The cons are that it may get hard to manage for big designs 2. Import the devices from the top top menu, e.g. "Device 1" where you have the basic nmos and pmos (e.g. as in this video around minute 17.44:

https://www.youtube.com/watch?v=uTlpT6Lszm4▾

https://www.youtube.com/watch?v=uTlpT6Lszm4

). a. Pros: fast and easy to generate devices, mostly if you have several fingers and want to include guard ring b. Cons: I managed to generate nmos and pmos for an inverter, but in the case of multiple fingers, it generates also the metals and the vias and I'm finding it difficult to connect or edit the generated cells Any opninions or advice on which approach is more convenient in the context of SKY130? I guess it's really personal but I'd like to read what people here are doing. Also, for the second case, do you know maybe how can I edit the generated cells if I want to remove or add some poligons to what is generated by default?

Hi, I run into an error below while trying to run iverilog simulation, /caravel_user_project/caravel/verilog/rtl/caravel_netlists.v41 Include file libs.ref/sky130_fd_io/verilog/sky130_ef_io.v not found is it due to wrong versioning of pdk? I installed openlane and built pdks via openlane repository

I wonder if anyone has figured out the following for ngspice: Run a transient analysis up to some time, save the circuit state, then use that state as the operating point for subsequent ac, noise, etc. analyses. This is frequently needed for SC circuits that need a few clock cycles to initialize, and it is supported by proprietary tools like spectre. For ngspice, I could find the thread linked below, where the question it asked at the bottom, but not answered. (I have been trying optran, but it seems that it is not meant to do what I am asking for.) https://sourceforge.net/p/ngspice/discussion/127605/thread/ca4d596065/

Hello. I am currently trying to launch xschem using https://github.com/iic-jku/osic-multitool and am getting the following error.

hayato@DESKTOP-931VA3D:~$ xschem
cd caravel_user_project_analog

^CUse 'exit' to close the program
open_pdks installation: using /home/hayato/pdk
SKYWATER_MODELS: /home/hayato/pdk/sky130A/libs.tech/ngspice
SKYWATER_STDCELLS: /home/hayato/pdk/sky130A/libs.ref/sky130_fd_sc_hd/spice
Tcl_AppInit() error: can not execute /usr/local/share/xschem/xschem.tcl, please fix:
invalid command name "image"
tcleval(): evaluation of script: wm withdraw . failed
         : invalid command name "wm"
tcleval(): evaluation of script: tk_messageBox -icon error -type ok -message        {Tcl_AppInit() err 1: can not execute /usr/local/share/xschem/xschem.tcl, please fix:
 invalid command name "image"} failed
         : invalid command name "tk_messageBox"

What I worked on:

cd osic-multitool/

export NGSPICE_VERSION=38

./iic-osic-setup.sh

cd

source iic-init.sh

There is no error on the way, but when xschem is executed after this, the above error appears. If anyone knows how to solve this problem, we would appreciate it if you could let us know.