Hi all, I'm attempting to use make a blackbox out of a custom made analog circuit that has multiple circuit blocks within it. I have drawn the gds in klayout and use magic to read the gds layout and generate the lef file. When I ran flow.tcl, I get stuck in the step: "running XOR on the layout using Klayout" (step 38 for me). I used

lef write bitfour_EESPFAL -tech

to generate the lef file in magic. Please tell me if I'm missing a step or my setup config is false. Any help is appreciated.

Hi, anyone know how can I simulate Phase Noise in ngspice ?

Does anyone know how I can open klayout with the pdk? I am trying with the following command:

Hi there, does anyone know what - "Can't find a schematic counterpart for top cell - use 'same_circuit' to establish a correspondence" error means

hi, is this error log means a crash ? [ERROR]: during executing openroad script /openlane/scripts/openroad/droute.tcl [ERROR]: Exit code: 1 [ERROR]: Last 10 lines: child killed: kill signal [ERROR]: Flow failed. this is the repo: https://github.com/mbaykenar/first_asic i have difficulties in global routing phase, i tried different config options, absolute or relative FP_SIZING, different FP_CORE_UTIL and PL_TARGET_DENSITY values. I always got congestion error. Then i added set ::env(GLB_RT_ALLOW_CONGESTION) 1 but this time again in global routing i got errors that i have written above any suggestion is appreciated: config.tcl parameters: set ::env(DESIGN_IS_CORE) 0 set ::env(CLOCK_PORT) "wb_clk_i" set ::env(CLOCK_NET) "pulpino_top_wrapper.clk" set ::env(CLOCK_PERIOD) "200" set ::env(PL_RESIZER_MAX_SLEW_MARGIN) 40 set ::env(PL_RESIZER_MAX_CAP_MARGIN) 40 set ::env(GLB_RESIZER_MAX_SLEW_MARGIN) 40 set ::env(FP_SIZING) absolute set ::env(DIE_AREA) "0 0 2500 2500" set ::env(FP_PIN_ORDER_CFG) $script_dir/pin_order.cfg set ::env(SYNTH_STRATEGY) "AREA 1" set ::env(PL_BASIC_PLACEMENT) 0 set ::env(PL_TARGET_DENSITY) 0.3 set ::env(FP_CORE_UTIL) {30} set ::env(PL_MACRO_CHANNEL) {30 30} set ::env(PL_MACRO_HALO) {10 10} set ::env(CELL_PAD) {2} set ::env(GLB_RESIZER_HOLD_MAX_BUFFER_PERCENT) {60} set ::env(ROUTING_CORES) {6} set ::env(GLB_RT_OVERFLOW_ITERS) {100} set ::env(GLB_RT_ALLOW_CONGESTION) 1 macro.cfg: pulpino_top.core_region_i.data_mem.open_ram_2k 1000 300 N pulpino_top.core_region_i.instr_mem.sp_ram_wrap_i.open_ram_2k 1000 1500 N

@User: I found an error in xschem (and please correct me if my version is just out of date): I have a symbol for the caravel project wrapper. It has vectors for some of the pins, like

io_out[26:0]

. Many of these pins don't require connections. But if I leave them unconnected on the wrapper symbol in my testbench schematic, then they are replaced in the nelist with a single wire

__UNCONNECTED_PIN__X

instead of an array. If I connect a wire to the pin going nowhere, it works just fine. So when there is no wire connected to a pin which is a bus, it should be generating as many

UNCONNECTED_PIN

nets in the call to the subcircuit as there are wires in the bus. Otherwise the simulation fails with a "not enough parameters in call" error. Clearly the workaround is to add a stub wire to the pin connection on the symbol, but that should be optional, and the behavior should be effectively the same in either case.

Hello, i am in process of hardening my user_proj_example module and encountered LVS errors during signoff stage. My design includes one SRAM macro and i am using wishbone ports for reading and writing to it. I appreciate any assistance you can provide. Thank yoy!

FWIW if you already have a login on another matrix server (i.e. matrix.org) then as an alternative you can just add the fossi-chat.org matrix server and public rooms to that account instead of having to go through the email registration process (again).

Is there anyway to access the tapeout files from old jobs which were submitted via the open galaxy efabless platform? i'd like to get the generated final .gds for a 2206Q project

@Stefan Schippers I know one can create a symbol from a schematic, but can one also automatically create a symbol from a SPICE netlist?