So in the std cells, the

nwell.pin

and

pwell.pin

are the connections from the

li

layer to the bulk (either the n-well or the p-substrate). I'm a bit surprised there is only 1 per cell though, I thought there would be a bunch equally spaced like the

mcon

between the

li

and

met1

carrying the power rails.

Hi everyone, I am looking for information about how to design a capacitor DAC layout for a 10-bit SAR ADC to get better matching. If anyone knows a good reference, I would really appreciate your help.

Good morning, I have a question about the

"SYNTH_STRATEGY"

parameter. What do the values from 0 to 4 represent? With AREA 0 do I get the smallest possible area? With DELAY 0 do I get the maximum clock speed?

@Norman Méndez can you repost your error here

hello i am trying to use reram 1.i tried to clone the repository and run install.sh file osdi file has been created further i am confused 2.i install latest version ngspice by enabling osdi anyone can please give the steps to sucessfully install everything and simulate so that i can use reram symbol in xschem Thank you

I try to harden an analog IP macro with digital parts. Using

flow.tcl

all steps work correctly, except last (STEP 35 LVS). There are the power pin that are not connected. Why? The verilog netlist is correct:

has anybody setup assura-quantus for parasitic extraction for the SKY130 PDK? I don't know which files to include for LPE config file, Black Box Cell View and Balck Box Cell View File and Probe Text File....I have added the paths to the rest of them i.e. to the

compilation.cmd

--> command file,

qrcTechFile

-->Tech cmd file and

layer_setup

--> layer setup file. I am not sure what to do with the lvsfile, RCXdspfINIT and RCXspiceINIT files. From what I understand the included

extview.trp

is supposed to be some sorta template for quantus setup but I am unable to load it, I get an error (I have attached a screenshot of the CIW error window message) If anyone could please guide how to setup assura quantus for post layout extraction for the SKY130 PDK, it would be greatly appreciated

Hi @aquiles viza, @Deni Alves, @Gabriel Maranhão, @Jorge Marin, @Atif Khan, @Akira Tsuchiya, and @Junbeom Park. @mehdi and @Boris Murmann would like to meet with the team leaders to discuss the next steps. I sent also an email to each team leader with this information. Can you join the Chipathon 2024 on Thursday 3rd October, at 11 am EST? Please let us know if it fits your schedule. Kind regards,

Hello guys, i have two file "lef" and "def", how can i visualize them in magic? I tried both command, "lef ready <file>" and "def ready <file>", but i get this error...

Out of curiosity, is there any downside to using LVT devices compared to standard devices? From an analog POV, I only see benefits from LVT devices: lower threshold -> lower overdrive -> better swing.