I have a doubt regarding the right way to set ports in a cell made with a hierarchical design. I have an AND cell made from a NAND cell plus an INVERTER cell. In the top level I connected the NAND output to the inverter input and made three ports: A and B as inputs in correspondence of NAND inputs and a OUT port in correspondence of the inverter output. I exported this design with the commands: 1) export all 2) ext2spice lvs 3) ext2spice -d My problem is I don't see any port in the AND subcircuit made from the layout. My questions: 1) What I have to do in order to make appear the ports in the subcircuit ? 2) Have I to put something else in the top level, example metal and contact, in correspondence of port label in order to make appear the port ?

error_dc_reram.PNG

My server has 48 cores, currently openlane only uses a maximum of 1 core to run, resulting in the running process being very slow. Is there any way to take full advantage of CPU cores to run openlane?

@Stefan Schippers Hi Stefan, I am trying to get S-parameters (loss, gain, noise factor) figures from a LNA circuit. This plot is basically magnitude(db) vs frequency. I could not find any command to do that in ngspice. Do you have any idea how to do it?

You can use set_max_delay for that. However, if you use it to constraint logic that has other larger paths going through it, those will be broken. It would be best to do report_check -through a_in -through a_out and see the full path. If that constrant can be adjusted its best. If the path is unconstrainted you should figure out why but can use the set_max_delay without fear of unconstraining constrained paths.

Hi, why if i have a project in Xschem and i use "Insert" Key to add subcircuits into my top circuit. When i push it to Git and clone it on another PC, the subcircuits there i had Inserted comes with bugs and i need to re-add all again (even if the directory skeleton stay the same)? How to fix it?

I have tried the same design on Synopsys Design Compiler and worked very well, but in Yosys it deletes all modules and keeps only the top while flattening the design. could anyone please help?

I am running OpenLane without Docker since I'm doing mostly analog design. When I try to run "./flow.tcl -design spm" I get the following error: "[ERROR STA-0402] repair_design -slew_margin is not a known keyword or flag. Error: resizer.tcl, 62 STA-0402 [ERROR]: during executing: "openroad -exit /mnt/HDD_WD/OpenLane/scripts/openroad/resizer.tcl |& tee >&@stdout /mnt/HDD_WD/OpenLane/designs/spm/runs/RUN_2021.12.12_15.55.21/logs/placement/8-resizer.log" [ERROR]: Exit code: 1 [ERROR]: Last 10 lines: child process exited abnormally" I'm running Version: 2021.12.10_01.41.40 All the fixes I found here were for the docker image, does anybody have the fix for the setup without it?

Is there any documentation on how to set up xschem for sky130 or gf180? I see the files in the pdk, just not sure if I'm supposed to copy the xschemrc or set PDK_ROOT or you know... how to properly launch xschem with the correct paths and libraries loaded.

Hi, I am trying to simulate a basic nfet circuit however, I am not sure why nothing happens when I click the Simulate button. I am trying to do transient analysis however nothing happens. I have also attached the spice file. I think it should be importing the .lib file for sky130 transistor models but it is not doing so. I have to do that manually and run ngspice manually from the terminal to make it work.