Hi, I am new to Xschem and am running a netlist simulation with ReRAM in sky130B pdk. The spice simulator is unable to get the model file for ReRAM from the /home/<user>/pdk_1/sky130B/libs.tech/ngspice/sky130.lib.spice tt library file. I searched for the ReRAM model definition but couldn't find it. Can someone help me with this? @Stefan Schippers

Hi, What is a Klayout FEOL error from the precheck? I looked on the reference https://github.com/efabless/mpw_precheck/blob/main/debug_precheck.md#how-to-load-marker-database-files for the errors, but only saw the Klayout drc errors? I checked the klayout_feol_check.xml file as suggested in the precheck log, but I'm unsure how to read it

<?xml version="1.0" encoding="utf-8"?>
<report-database>
 <description>SKY130 DRC runset</description>
 <original-file/>
 <generator>drc: script='/home/connie/mpw_precheck/checks/tech-files/sky130A_mr.drc'</generator>
 <top-cell>user_analog_project_wrapper</top-cell>
 <tags>
 </tags>
 <categories>
  <category>
   <name>dnwell.2</name>
   <description>dnwell.2 : min. dnwell width : 3.0um</description>
   <categories>
   </categories>
  </category>
  <category>

are there any resources to decipher this? Thanks!

Is there a list somewhere of all available TCL commands ? I need to find an instance name from a "glob". ( actual instance name is something like

gpio\[0\].gpio_I.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.pad_I

) but I'd like to find the complete name using just the prefix

gpio\[0\]

.

Hi @Stefan Schippers, I'm trying to invoke xschem to output a spice netlist from a bash script - something I have always done for LVS runs - but I seem to be getting an error which I've not seen before when I have an instance of xschem already running. How can I fix this? Cheers, Tom

tom@tom-workstation:/media/tom/Storage/Linux/repos/discrete-buck$ xschem --rcfile=$PROJECT_ROOT/xschemrc -n -q -o .  --tcl "set top_subckt 0" "sch/tb_sbmix2.sch"
setup_tcp_xschem: problems listening to TCP port: 2021
couldn't open socket: address already in use

秋田さんから、先日Googleでデモしてもらった、P&RのMLの最適化の資料をシェアしていただきました。 https://ai.googleblog.com/2020/04/chip-design-with-deep-reinforcement.html

@User: I found an error in xschem (and please correct me if my version is just out of date): I have a symbol for the caravel project wrapper. It has vectors for some of the pins, like

io_out[26:0]

. Many of these pins don't require connections. But if I leave them unconnected on the wrapper symbol in my testbench schematic, then they are replaced in the nelist with a single wire

__UNCONNECTED_PIN__X

instead of an array. If I connect a wire to the pin going nowhere, it works just fine. So when there is no wire connected to a pin which is a bus, it should be generating as many

UNCONNECTED_PIN

nets in the call to the subcircuit as there are wires in the bus. Otherwise the simulation fails with a "not enough parameters in call" error. Clearly the workaround is to add a stub wire to the pin connection on the symbol, but that should be optional, and the behavior should be effectively the same in either case.

@Tim Edwards @Harald Pretl @Boris Murmann we have a question about introducing a separate symbol and pycell of a guard ring and also a global symbol

sub!

in our PDK. Electrically these guard ring devices are just ptap1 and ntap1 with the respective resistance. The

w

and

l

parameters define the guard ring size while

d

define the ring width. There are two purposes of this device: (1) to annotate on the schematic the use of guard ring and let the layout designer know that a specified bloc should be isolated/shielded by a guard ring; (2) have a dedicated entry in the netlist which will allow auto generation of a guard ring based on the size. Right now the devices are netlisted as follows:

XR1 net1 net2 ntap1 R=17.8 w=6e-6 l=6e-6 d=0.31e-6
XR2 net3 sub! ptap1 R=17.8 w=6e-6 l=6e-6 d=0.31e-6

While a regular ptap1/ntap1 devices are annotated without

d

parameter

XR1 net1 net2 ntap1 R=268.2 w=0.78e-6 l=0.78e-6 
XR2 net3 sub! ptap1 R=268.2 w=0.78e-6 l=0.78e-6

Actually

w

,

l

and

d

are not used by the simulator which only considers

R

, however based on these params a layout cell can be generated. So the question is if you consider useful this kind of approach ?

<!channel>: The first Chipalooza test chip has returned from fabrication, and I will be working on both testing some parts that I have in hand myself, and getting some parts out to the designers who have designs on the chip. I have not tested much so far, but what I have tested looks good (to the extent that I can do testing on my desk, which means all under nominal conditions; characterization will happen later). I looked at the two op-amps (@Thomas Dexter and @Luis Henrique Rodovalho); both of them appear to be operating to spec. I did a simple test on the comparator (@Andrew Kang) which also appears to be working although I don't have any specific performance measurements. I updated the repository https://github.com/RTimothyEdwards/chipalooza_projects_1 for the test chip with a new directory

firmware/

containing the test setups for four of the circuits, and software utilities for configuring them. In the next few days I hope to take a few simple measurements from all of the circuits on the chip. In addition to the ones mentioned above, that means the temperature sensor (@Or Dicker), the crystal oscillators (@htamas and @Brady Etz), the brownout/overvoltage/POR circuits (@Robin Tsang) and the overvoltage detector (@Lucas Daudt Franck and @William Carrara Orlato). I will keep everyone informed about when I can get additional parts packaged and sent out to the designers.

The klayout lyp file colors are 🤮

Is your setup file correct?

.../netgen/sky130A_setup.tcl

Check your netgen output for error messages (ie. can't find file, etc.) Also, I recommend putting the layout netlist first and the schematic netlist second. From the setup file.

# NOTE:  In accordance with the LVS manager GUI, the schematic is
# always circuit2, so some items like property "par1" only need to
# be specified for circuit2.