Hello! I would like to run a simulation with Verilator+Cocotb, generate a VCD, then perform power analysis on that VCD. Does anyone know of a good flow for this? • I see report_power from OpenSTA, but that's just static analysis: https://github.com/The-OpenROAD-Project/OpenSTA/blob/1c7f022c/doc/ChangeLog.txt#L106-L126 • Vivado can do power analysis only on SAIF files, not VCD files. I see Synopsys's vcd2saif online, but no free/open-source solutions • Can I synthesize for sky130, then run ngspice to match my VCD somehow? (I feel like that is overkill though) Thanks in advance!

Hello all, I am working on a CMOS voltage reference design for chipalooza, time is getting short and my op simulations are getting unstable 😕 my work is here (https://github.com/adankvitschal/sky130_ak_ip__cmos_vref) in case anyone would like to take a look (altough current circuit is not commited yet, just the core part) 1. Just looking at these outputs, can anyone say if the problem is with simulation parameters or circuit startup? (there are vref vs temp and vref vs supply). The problems started when I added a 1M resitor and 0.1pf capacitor as a load at vref output. 2. Also, I am having a hard time finding a decent technique to generate scaled versions of my reference voltage, should I just use gigantic resitors for this? my current budget is around 1uA, so, R>1M, is this ok?

@Stefan Schippers: Here's a new question for you. I've been working on this CACE system for automatic characterization. It was developed on the Efabless platform years ago when we were using Electric for schematic entry and hadn't heard of xschem. So I was trying to introduce variables and equations into the netlists to be resolved by direct substitution. For the variables I used the usual standard of

${name}

; for the equations I introduced a stack notation with the odd looking variables

${*}

${/}

${+}

${-}

and suchlike; so

${A} ${B} ${+} 2 ${/}

would resolve to

(A+B)/2

. This notation can get rather cumbersome. I think I can replace the whole system with just a call to xschem to generate a netlist if I pass all the variable names to xschem, but I would also need to replace the stack notation stuff. I think it is a straightforward matter of replacing it with calls to

tcleval

. I've attached a schematic for a CACE testbench. How should I write the device parameters with

tcleval

(or any other syntax that works) so that xschem would do the work of variable substitution and produce the output I'm currently doing with python code inside CACE? (FYI, the variable notation on pins is also being handled inside CACE but I do not think this is needed and I can dispense with it altogether).)

Hi everyone, I am running innovus for Sky130 pdk using a riscv processor and openram generated sram memory. We are facing the following issue. Attached are both sky130_tech.lef files and sram_tech.lef files. Can someone help us out ?

Hi, I am new to Xschem and am running a netlist simulation with ReRAM in sky130B pdk. The spice simulator is unable to get the model file for ReRAM from the /home/<user>/pdk_1/sky130B/libs.tech/ngspice/sky130.lib.spice tt library file. I searched for the ReRAM model definition but couldn't find it. Can someone help me with this? @Stefan Schippers

Hello everyone. I am working on an open source wire bonding application for QFN packages, although the algorithm I constructed can be generalized for all sorts of packages. I was wondering if anyone has experience using proprietary software, so I have something to compare it with.

@Tim Edwards @Harald Pretl @Boris Murmann we have a question about introducing a separate symbol and pycell of a guard ring and also a global symbol

sub!

in our PDK. Electrically these guard ring devices are just ptap1 and ntap1 with the respective resistance. The

w

and

l

parameters define the guard ring size while

d

define the ring width. There are two purposes of this device: (1) to annotate on the schematic the use of guard ring and let the layout designer know that a specified bloc should be isolated/shielded by a guard ring; (2) have a dedicated entry in the netlist which will allow auto generation of a guard ring based on the size. Right now the devices are netlisted as follows:

XR1 net1 net2 ntap1 R=17.8 w=6e-6 l=6e-6 d=0.31e-6
XR2 net3 sub! ptap1 R=17.8 w=6e-6 l=6e-6 d=0.31e-6

While a regular ptap1/ntap1 devices are annotated without

d

parameter

XR1 net1 net2 ntap1 R=268.2 w=0.78e-6 l=0.78e-6 
XR2 net3 sub! ptap1 R=268.2 w=0.78e-6 l=0.78e-6

Actually

w

,

l

and

d

are not used by the simulator which only considers

R

, however based on these params a layout cell can be generated. So the question is if you consider useful this kind of approach ?

<!channel>: The first Chipalooza test chip has returned from fabrication, and I will be working on both testing some parts that I have in hand myself, and getting some parts out to the designers who have designs on the chip. I have not tested much so far, but what I have tested looks good (to the extent that I can do testing on my desk, which means all under nominal conditions; characterization will happen later). I looked at the two op-amps (@Thomas Dexter and @Luis Henrique Rodovalho); both of them appear to be operating to spec. I did a simple test on the comparator (@Andrew Kang) which also appears to be working although I don't have any specific performance measurements. I updated the repository https://github.com/RTimothyEdwards/chipalooza_projects_1 for the test chip with a new directory

firmware/

containing the test setups for four of the circuits, and software utilities for configuring them. In the next few days I hope to take a few simple measurements from all of the circuits on the chip. In addition to the ones mentioned above, that means the temperature sensor (@Or Dicker), the crystal oscillators (@htamas and @Brady Etz), the brownout/overvoltage/POR circuits (@Robin Tsang) and the overvoltage detector (@Lucas Daudt Franck and @William Carrara Orlato). I will keep everyone informed about when I can get additional parts packaged and sent out to the designers.

I have a synthesized design, obtained the GDS file using OpenROAD with a 45nm technology and I would like to have it taped out. Can anyone walk me through the process?

Hi, What is the purpose of io_oeb in user_project_wrapper?