‼️ Important ‼️ Efabless has shutdown operation due to funding challenges: https://efabless.com/notice Given the current circumstances and uncertainties, we (a group of individuals) have decided to set up a new communication platform called FOSSi Chat. FOSSi Chat uses Matrix, an open protocol for decentralised, secure communications that is already the platform of choice for a large number of open source communities. We are currently in the process of reaching out to the FOSSi Foundation to take ownership of FOSSi Chat. Let's make sure the community as a whole finds a new place, please join FOSSi Chat: fossi-chat.org

Hi, I'm a student who just started with IC design. Since the school provides Cadence tools for free, I'm currently using Virtuoso for schematic design and simulation with the Sky130 PDK (currently using

efabless/main

from Github). What I want to simulate is a simple

nfet

simulation, but I keep encountering many errors. Since the Spectre simulator supports both Spectre and Spice, I thought it would work without issue. I know Sky130 is friendly to the open-source tools, but is it intentionally incompatible with Virtuoso? Does anyone have any insights or comments on this? Please share your experiences with getting it to work with Virtuoso. I would greatly appreciate any advice on the Sky130 PDK ecosystem and its compatibility with Cadence tools.

Hi everyone, I am looking for information about how to design a capacitor DAC layout for a 10-bit SAR ADC to get better matching. If anyone knows a good reference, I would really appreciate your help.

Hi @aquiles viza, @Deni Alves, @Gabriel Maranhão, @Jorge Marin, @Atif Khan, @Akira Tsuchiya, and @Junbeom Park. @mehdi and @Boris Murmann would like to meet with the team leaders to discuss the next steps. I sent also an email to each team leader with this information. Can you join the Chipathon 2024 on Thursday 3rd October, at 11 am EST? Please let us know if it fits your schedule. Kind regards,

Hello, This is related to the IP hardening process. From the tutorials on efabless.com, I understand that IP hardening is 2-step process (1: Harden your design, 2: Instantiate the netlist within user_project_wrapper and then harden the complete wrapper). Can we simply instantiate our custom RTL in user_project_wrapper and harden only once?

Hi, I was trying to compile the sky130 64x512_8 SRAM using

sram_compiler.py

and it gave me the following error. I also set

netlist_only = True

. The error is not thrown for lower number of words (eg: 16, 32) but occurs for higher values such as 128, 256. Is this a configuration issue or is this a bug? If it is a config issue, perhaps the example file should be changed.

DELAY: Writing stimulus...
ERROR: file simulation.py: line 605: Could not find bl net in timing paths.

hello does anyone know how I can do a mixed signal simulation in xschem?

@Stefan Schippers Hi Stefan, I am trying to get S-parameters (loss, gain, noise factor) figures from a LNA circuit. This plot is basically magnitude(db) vs frequency. I could not find any command to do that in ngspice. Do you have any idea how to do it?

Good morning, I have a question about the

"SYNTH_STRATEGY"

parameter. What do the values from 0 to 4 represent? With AREA 0 do I get the smallest possible area? With DELAY 0 do I get the maximum clock speed?

Hi all, I'm getting an error when trying to run openlane on a simple version of the caravel_wrapper with the

user_project_wrapper.def

as a template. Openlane is failing at step 4 (IO placement) telling me that there are 416 IO pins (looks about right according to the verilog), but only 28 "positions" (not sure where this number 28 is coming from). If i look at the def. there 1134 lines with the word

PORT

on them so I have no idea why I'm getting this error. Can anyone offer any insight? Thanks in advance.

OpenROAD 6f9b2bb8b808b1bb5831d4525d868212ae50517a 
This program is licensed under the BSD-3 license. See the LICENSE file for details.
Components of this program may be licensed under more restrictive licenses which must be honored.
[INFO]: Reading ODB at '/media/tom/Storage/Linux/repos/projects/openwave-caravel/openwave/cells/caravel/runs/RUN_2023.12.07_19.53.49/tmp/floorplan/3-initial_fp.odb'…
define_corners Typical
read_liberty -corner Typical /home/tom/repos/edalibs/pdks/gf180mcu/gf180mcuD/libs.ref/gf180mcu_fd_sc_mcu7t5v0/liberty/gf180mcu_fd_sc_mcu7t5v0__tt_025C_5v00.lib
Using 1e-12 for capacitance...
Using 1e+00 for resistance...
Using 1e-09 for time...
Using 1e+00 for voltage...
Using 1e-03 for current...
Using 1e-06 for power...
Using 1e-06 for distance...
Reading design constraints file at '/openlane/scripts/base.sdc'…
[INFO]: Setting output delay to: 8.0
[INFO]: Setting input delay to: 8.0
[INFO]: Setting load to: 0.07291
[INFO]: Setting clock uncertainty to: 0.25
[INFO]: Setting clock transition to: 0.15
[INFO]: Setting timing derate to: 5.0 %
Found 0 macro blocks.
[ERROR PPL-0024] Number of IO pins (416) exceeds maximum number of available positions (28).
Error: ioplacer.tcl, 51 PPL-0024