I get Utilization exceeds 100% what should be the maximum area in config.json

Manish Mahajan

02/29/2024, 6:23 AM

I get Utilization exceeds 100% what should be the maximum area in config.json

Manish Mahajan

02/29/2024, 6:23 AM

INFO GPL-0002] DBU: 1000 [INFO GPL-0003] SiteSize: 460 2720 [INFO GPL-0004] CoreAreaLxLy: 5520 10880 [INFO GPL-0005] CoreAreaUxUy: 3794080 2747200 [INFO GPL-0006] NumInstances: 2342523 [INFO GPL-0007] NumPlaceInstances: 2192335 [INFO GPL-0008] NumFixedInstances: 150188 [INFO GPL-0009] NumDummyInstances: 0 [INFO GPL-0010] NumNets: 2192713 [INFO GPL-0011] NumPins: 6742083 [INFO GPL-0012] DieAreaLxLy: 0 0 [INFO GPL-0013] DieAreaUxUy: 3800000 2760000 [INFO GPL-0014] CoreAreaLxLy: 5520 10880 [INFO GPL-0015] CoreAreaUxUy: 3794080 2747200 [INFO GPL-0016] CoreArea: 10366712499200 [INFO GPL-0017] NonPlaceInstsArea: 192950054400 [INFO GPL-0018] PlaceInstsArea: 23539650140800 [INFO GPL-0019] Util(%): 231.38 [INFO GPL-0020] StdInstsArea: 23539650140800 [INFO GPL-0021] MacroInstsArea: 0 [ERROR GPL-0301] Utilization exceeds 100%. Error: gpl.tcl, 71 GPL-0301

Manish Mahajan

02/29/2024, 6:24 AM

"DIE_AREA": "0 0 3800 2760", in config.json

Vijayan Krishnan

02/29/2024, 6:25 AM

share complete config.json what you used

Manish Mahajan

02/29/2024, 6:27 AM

config.json

Manish Mahajan

02/29/2024, 6:31 AM

The utilization is Util(%): 231.38

Vijayan Krishnan

02/29/2024, 6:33 AM

what is the register size you're using? Maybe converting those register into hard macros will resolve the issue

Manish Mahajan

02/29/2024, 6:34 AM

where can I find the register size, is it during synthesis

Vijayan Krishnan

02/29/2024, 6:36 AM

In verilog file *_register.v Check DFF count synthesis report

Manish Mahajan

02/29/2024, 6:38 AM

It has mapped 208 $_DFF_PN0_ cells to \sky130_fd_sc_hd__dfrtp_2 cells. 208 DFF and mapped 27801 $_DFF_PN0_ cells to \sky130_fd_sc_hd__dfrtp_2 cells

Vijayan Krishnan

02/29/2024, 6:40 AM

if it is open design mean, raise a github issue with test case

Manish Mahajan

02/29/2024, 6:41 AM

It has generated the issue reproducible where should that be uploaded

Vijayan Krishnan

02/29/2024, 6:42 AM

https://github.com/The-OpenROAD-Project/OpenLane/issues/new/choose follow the template and file an issue

Vijayan Krishnan

02/29/2024, 6:44 AM

do you have any

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reg [63:0] Memory[0:127];

such declarations in verilog code?

Manish Mahajan

02/29/2024, 6:45 AM

I have them as registers There are many registers [31:0] but no memories

Vijayan Krishnan

02/29/2024, 6:46 AM

check this doc: https://openlane.readthedocs.io/en/latest/tutorials/openram.html

Manish Mahajan

02/29/2024, 6:53 AM

Thanks

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